Example Of A Block Dma Operation For Rfm-5565 - GE PCIE-5565PIORC* Hardware Reference Manual

3.4 Example of a Block DMA Operation for RFM-5565

1. Base Address Register 0 stores the starting address of the Local Control and
Configuration registers, which include the DMA Control registers. The value
in this register is PCIBAR0.
2. There are six DMA registers that must be configured to set up the DMA
cycle. These DMA registers will remain unchanged after the DMA cycle.
DMA channel 0 mode setting:
Bit 9 set to 0 indicates the use of normal
Block DMA (not Scatter/Gather mode).
DMA channel 0 PCI starting address:
Set to the starting address of the PC
memory (for either source or destination
transfer).
DMA channel 0 local starting address:
Set to the starting address of the local
(RFM) memory (for either source or
destination transfers).
NOTE: The first local (RFM) memory
location is at $0.
DMA channel 0 transfer size:
Set to the number of bytes to be
transferred (maximum $7FFFFF).
DMA channel 0 Descriptor Pointer:
Set to $0 for PCI‐to‐Local
or set to $8 for Local‐to‐PCI.
DMA channel 0 PCI DAC upper address:
This register is set to $0 when using 32‐bit
addresses.
3. To initiate and monitor the transfer, access DMACSR0 as follows:
DMA channel 0 Command/Status register:
DMACSR0 at PCIBAR0 + offset $A8.
Write $0003 to start the transfer, then poll the same register.
When Bit 4 is high (1), the DMA cycle is complete.
NOTE
Polling read cycles take priority over the DMA cycles. Overly aggressive polling will slow the DMA
transfer. Rather than polling for the DMA done condition, the user can choose to enable the PCI
interrupt on DMA done by setting Bit 18 of the INTCSR at offset $68 to high (1). Once the interrupt is
enabled, the user software routine waits for the interrupt to occur.
4. After the DMA is finished, clear the DMA completion bit with a write to
DMACSR0 as follows. This is necessary when using DMA interrupts.
DMA channel 0 Command/Status register:
DMACSR0 at PCIBAR0 + offset $A8.
Write $8 to clear the DMA completion bit before attempting
another DMA.
DMAMODE0 at PCIBAR0 + offset $80
DMAPADR0 at PCIBAR0 + offset $84
DMALADR0 at PCIBAR0 + offset $88
DMASIZ0 at PCIBAR0 + offset $8C
DMADPR0 at PCIBAR0 + offset $90
DMADAC0 at PCIBAR0 + offset $B4
Programming 61