Table 3-22 Pci Interrupt Line; Table 3-23 Pci Interrupt Pin; Table 3-24 Msi Capability Structure; Table 3-25 Message Control Bit Definition - GE PCIE-5565PIORC* Hardware Reference Manual

38 PCIE-5565PIORC Reflective Memory Board

Table 3-22 PCI Interrupt Line

Bit Description
7:0 Interrupt Line Routing Value. Value indicates which input of the system
interrupt controller(s) is connected to each interrupt line of the device.
*NOTE: This register will be altered by the system BIOS during the system boot process.

Table 3-23 PCI Interrupt Pin

Bit Description
7:0 Interrupt Pin Register. Indicates which interrupt pin the
device uses. The following values are decoded (the
Reflective Memory supports only INTA#).
1 = INTA#
2 = INTB#
3 = INTC#
4 = INTD#

Table 3-24 MSI Capability Structure

Offset 31::16
0x050 Message Control
0x054
0x058
0x05C

Table 3-25 Message Control bit definition

Bit(s) Field
15:9 Reserved
8 Mask Capability
7 64-bit Address Capability Not Supported. Hardwired to 0
6:4 Multiple Message Enable Indicates the number of MSI signals
3:1 Multiple Message
Capable
0 MSI Enable
PCI Interrupt Line: PCIILR, Offset $3C
PCI Interrupt Pin: PCIIPR, Offset $3D
Message Address
Message Upper Address
Reserved
Message Control bit definition: Offset 0x050
Description
Not Supported. Hardwired to 0
allocated by system software.
- 000: 1MSI allocated
- 001: 2 MSI allocated
- 010: 4 MSI allocated
- 011: 8 MSI allocated
- 100: 16 MSI allocated
- 101: 32 MSI allocated
- 110: Reserved
- 111: Reserved
Indicates the number of requested MSI
messages
- 010:4 MSI allocated
1= MSI Enabled
Read Write
Yes Yes
Read Write
Yes No
15:8 7:0
0x78 (next cap ptr) 0x05 (capability ID)
Message Data
R/W
R/W
R
R
R/W
R
R/W
*Value after
PCI Reset
$0
Value after
PCI Reset
$1