Table 3-6 Pci Class Code Register; Table 3-7 Pci Cache Line Size Register; Table 3-8 Pci Latency Timer Register; Table 3-9 Pci Header Type Register - GE PCIE-5565PIORC* Hardware Reference Manual

Table 3-6 PCI Class Code Register

Bit Description
7:0 Register Level Programming Interface. None defined.
15:8 Subclass Code
23:16 Base Class Code
Base Class Code of $02 equals Network Controller. Subclass Code of $80 equals other network controller.

Table 3-7 PCI Cache Line Size Register

Bit Description
7:0 System Cache Line Size. Not applicable to PCI Express.
*NOTE: This register can be altered by the system BIOS during the system boot process.

Table 3-8 PCI Latency Timer Register

Bit Description
7:0 PCI Bus Latency Timer. Not applicable to PCI Express.
*NOTE: This register can be altered by the system BIOS during the system boot process.

Table 3-9 PCI Header Type Register

Bit Description
6:0 Configuration Layout Type. Specifies layout of bits $10
through $3F in Configuration Space. Only one encoding, $0,
is defined. All other encodings are reserved.
7 Header Type.
Writing a one (1) indicates multiple functions.
Writing a zero (0) indicates single function.
PCI Class Code: Offset $09
PCI Cache Line Size: Offset $0C
PCI Latency Timer: Offset $0D
PCI Header Type: Offset $0E
Read Write
Yes No
Yes No
Yes No
*Value after
Read Write
PCI Reset
Yes Yes $0
*Value after
Read Write
PCI Reset
Yes Yes $00
Read Write
Yes No
Yes No
Programming 33
Value after
PCI Reset
$0
$80
$02
Value after
PCI Reset
$0
0