Table 3-38 Interrupt Control And Status Register; Table 3-39 Intcsr Interrupt Enables; Table 3-40 Intcsr Interrupt Status - GE PCIE-5565PIORC* Hardware Reference Manual

Table 3-38 Interrupt Control and Status Register

Bit Description
7:0 Reserved
8 PCI Interrupt Enable. Writing a one (1) enables PCI interrupts.
10:9 Reserved
11 Local Interrupt Input Enable.
Writing a one (1) enables a local interrupt (i.e., RFM interrupts) to
assert a host Interrupt.
14:12 Reserved
15 Local Interrupt Input Active.
When set to a one (1), indicates the Local interrupt input is active.
16 Reserved
17 Reserved
18 Local DMA Channel 0 Interrupt Enable.
Writing a one (1) enables DMA Channel 0 interrupts.
Clearing the DMA status bit also clears the interrupt.
20:19 Reserved
21 DMA Channel 0 Interrupt Active.
Reading a one (1) indicates the DMA Channel 0 interrupt is active.
23:22 Reserved
27:24 Reserved
31:28 Reserved
The PCI Interrupt Enable (Bit 8) functions as a global PCI interrupt enable. It must
be set high (1) in addition to other enable bits before any primary or secondary
tier interrupt source will result in a PCI interrupt.
Table 3‐39 on page 45 summarizes the INTCSR Interrupt Enables that pertain to
RFM‐5565 operation.

Table 3-39 INTCSR Interrupt Enables

Enable the interrupt source:
Global PCI interrupt enable for all sources
Any second tier int. through Local Int. Input (LINTi#) 11
Local DMA Channel 0 interrupt
Table 3‐40 on page 45 summarizes the INTCSR Interrupt Status bits that pertain to
RFM‐5565 operation.

Table 3-40 INTCSR Interrupt Status

To check the assertion of the following interrupt source:
Any second tier int. through Local Int. Input (LINTi#)
Local DMA Channel 0 interrupt
INTCSR: BAR0/1 Offset $68
Set the following Bit high (1):
8
18
Check for a high (1) at Bit:
15
21
Value after
Read Write
PCI Reset
Yes No $00
Yes Yes 1
Yes No 0
Yes Yes 0
Yes No 0
Yes No 0
Yes No 1
Yes No 0
Yes Yes 0
Yes No 0
Yes No 0
Yes No $0
Yes No $f
Yes No $0
Programming 45