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Local Control and Status Register 1 Bit Definitions
Bit 31:
Status LED – The board contains a user defined RED status
LED. Setting this bit low (0) turns OFF the LED. The default
state of this bit after reset is high (1) and the LED will be ON.
Bit 30:
Transmitter Disable – Setting this bit high (1) will manually
turn OFF the board's transmitter. The default state of this bit
after reset is low (0) and the transmitter is enabled. When
turning the board's transmitter back ON by setting this bit
back to low (0), an unspecified amount of time must be
allowed to provide for the turn‐on time of the optics.
Bit 29:
Dark‐on‐Dark Enable – When this bit is set high (1), the
board's transmitter will be turned OFF if the board's receiver
does not detect a signal or if the receiver detects invalid data
patterns. The dark‐on‐dark feature is useful in hub
configurations.
Bit 28:
Loopback Enable – When this bit is set high (1), the fiber
optic transmitter and receiver are disabled and the transmit
signal is looped back to the receiver circuit internally. This
allows basic functional testing with or without an external
cable.
Bit 27:
Local Memory Parity Enable – When this bit is set high (1),
parity checking is enabled when reading from the RFM‐5565
SDRAM. Note that parity works only on 32‐bit and 64‐bit
accesses. Byte (8‐bit), Word (16‐bit), and 24‐bit memory write
accesses are inhibited while parity is enabled.
Bit 26:
Redundant Mode Enabled – When this bit is set high (1),
redundant mode of network transfers has been enabled. This
bit is read‐only. Redundant mode is enabled by setting switch
S1 position 1 in the ON position.
Bit 25:
Rogue Master 1 Enabled – When this bit is set high (1), the
board is operating as Rogue Master 1. This bit is read‐only.
Rogue Master 1 operation is enabled by setting switch S1
position 6 in the ON position.
Bit 24:
Rogue Master 0 Enabled – When this bit is set high (1), the
board is operating as Rogue Master 0. This bit is read‐only.
Rogue Master 0 operation is enabled by setting switch S1
position 5 in the ON position.
Bit 23:
Reserved – This bit is reserved.
Bits 22 and 19:
Window 1 and Window 0 – The PCI PIO window size is
selected by setting S1 switch positions 3 and 4. Bit 19
(Window 0) is connected to S1 switch position 3 ('1' when
ON, '0' when OFF). Bit 22 (Window 1) is connected to S1
switch position 4 ('1' when ON, '0' when OFF). These two
bits indicate the memory PCI PIO window size as defined in
the following table. The two bits are read only.
Programming 51
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