Table 3-48 Dma Channel 0 Pci Dual Address Cycles Upper Address; Table 3-49 Pci Pio Direct Slave Local Address Range; Table 3-50 Pci Pio Direct Slave Local Base Address (Remap) - GE PCIE-5565PIORC* Hardware Reference Manual

48 PCIE-5565PIORC Reflective Memory Board

Table 3-48 DMA Channel 0 PCI Dual Address Cycles Upper Address

Bit Description
31:0 Upper 32 Bits for 64-bit addressing during DMA Channel 0
Cycles. If set to $0, the DMA performs a 32-bit address DMA
Channel 0 access.

Table 3-49 PCI PIO Direct Slave Local Address Range

Bit Description
0 Memory Space Indicator. A zero (0) indicates Local Address
Space 1 maps into PCI Memory space.
3:1 Reserved
31:4 Range. Specifies which PCI Address bits to use for decoding a PCI
access to Local Address Space 1. Each bit corresponds to a PCI
Address bit. Bit 31 corresponds to address bit 31. Write one (1) to
all bits that must be included in decode and zero (0) to all others.
(Used in conjunction with PCIBAR3).
NOTE: LAS1RR range must be power of 2. The LAS1RR range value is two's complement of the range.

Table 3-50 PCI PIO Direct Slave Local Base Address (Remap)

Bit Description
0 Local Address Space 1 Enable. A one (1) enables decoding of PCI
addresses for PIO addresses for PIO Direct Slave access to Local
Address Space 1 (PCIBAR3).
3:1 Reserved
31:4 Remap PCIBAR3 Base Address to Local Address Space 1 Base
Address. The PCIBAR3 base address translates to the Local
Address Space 1 Base Address programmed in this register. A
Direct Slave access to an offset from PCIBAR3 maps to the same
offset from this Local Base Address.
NOTE: Remap Address value must be a multiple of the LAS1RR range.
DMADAC0: BAR0/1 Offset $B4
LAS1RR: BAR0/1 Offset $F0
LAS1BA: BAR0/1 Offset $F4
Value after
Read Write
PCI Reset
Yes Yes $0
Value after
Read Write
PCI Reset
Yes No 0
Yes No $0
Yes No $FFE0000
(for 2 MB)
$FF00000
(for 16 MB)
$FC00000
(for 64 MB)
$F800000
(for 128 MB)
$F000000
(for 256 MB)
Value after
Read Write
PCI Reset
Yes No 1
Yes No $0
Yes Yes $0