GE PCIE-5565PIORC* Hardware Reference Manual page 52

52 PCIE-5565PIORC Reflective Memory Board
Bits 21 and 20: Config 1 and Config 0 – These two bits indicate the installed
memory size as defined in the following table. The two bits
are read‐only.
Bit 18: Delay TX from PCI Write – When this bit is set high (1), the
board is operating with reduced PCI write bandwidth. This
bit is read‐only. This mode is enabled by setting switch S1
position 2 in the ON position. Data received on the PCI bus
will be delayed before it is written to memory or transmitted
on the network. This prevents the node from using full
network bandwidth. This setting is normally OFF.
Bits 17 and 16: Offset 1 and Offset 0 – When the host PCI system writes to
the onboard memory and initiates a packet over the network,
Offset 1 and Offset 0 will apply an offset to the network
address as it is sent or received over the network. The offset
does not appear on local access to the memory, and the offset
does not alter network packets as they pass through the
board. Offset 1 and Offset 0 provide four possible binary
increments of 64 MByte each through the 256 MByte network
address range. When the address and offset exceeds the
256 MByte network address range, the address bits beyond
256 MByte will be truncated. This causes the write to wrap
around into a lower memory location. Offsets 1 and 0's bits
correspond to the network address bits A27 and A26
respectively.
Window 1 Window 0
0 0
0 1
1 0
1 1
Config 1 Config 0
0 0
0 1
1 0
1 1
Offset 1 Offset 0
0 0
0 1
1 0
1 1
PCI PIO Window Size
default = installed memory size
64 MByte
16 MByte
2 MByte
Memory Size
64 MByte
128 MByte
256 MByte
Reserved
Offset Applied
$0
$4000000
$8000000
$C000000