Local Interrupt Control Registers; Table 3-53 Local Interrupt Status Register - GE PCIE-5565PIORC* Hardware Reference Manual

54 PCIE-5565PIORC Reflective Memory Board

3.3.6 Local Interrupt Control Registers

The RFM‐5565 contains a number of sources for the interrupt. The second tier of
interrupts is controlled by two registers called the LISR as shown in Table 3‐53 on
page 54 and the LIER shown in Table 3‐54 on page 57. All Local Interrupts are
logically "ORed" together into the single interrupt called the LINTi#. The LINTi#
line is, in turn, controlled by Bit 11 of the Local Configuration register (INTCSR at
offset $68 to Base address 0). The control and status of local interrupts are
implemented in the two local registers (LISR and LIER). The bit functions of these
two registers mirror each other.
Local Interrupt Status Register
Local Interrupt Status Register (LISR) BAR2 (Offset $10): This is a 32‐bit register
containing a group of interrupt status flags. The LIER contains a corresponding
group of enables. Before any local interrupt can cause an interrupt on the LINTi#
line, the Status Bit, its Enable and the Global Enable must be asserted.

Table 3-53 Local Interrupt Status Register

Bit 31 Bit 30 Bit 29
Bit 23 Bit 22 Bit 21
Bit 15 Bit 14 Bit 13
Auto Clear Global Local
Flag Interrupt Memory
Enable Parity Error
Bit 07 Bit 06 Bit 05
Pending Rogue Packet TX FIFO Full Reserved
Net. Int. 4 Fault
Local Interrupt Control Register Bit Definitions
Bits 31 through 16: Reserved ‐ These bits are reserved.
Bit 15: Auto Clear Flag – This bit is a read‐only status indicator of
the corresponding bit in the LIER Register. When this bit is
high (1), the Global Interrupt Enable (Bit 14) will
automatically be cleared as this register (LISR) is being read.
Clearing the Global Interrupt Enable de‐asserts the LINTi#
and, in turn, releases the PCI Interrupt.
Bit 14: Global Interrupt Enable – This bit must be set high (1) in
addition to any interrupt flag and its associated enable bit in
the LIER before the LINTi# line is asserted and a PCI
interrupt can result. If the Auto Clear enable bit in the LIER is
LISR: BAR2 Offset $10
Bit 28 Bit 27 Bit 26
Reserved
Bit 20 Bit 19 Bit 18
Reserved
Bit 12 Bit 11 Bit 10
Memory Latched Sync RX FIFO Full RX FIFO
Write Loss
Inhibit
Bit 04 Bit 03 Bit 02
Reset Node Pending
Request Net. Int. 3
Bit 25 Bit 24
Bit 17 Bit 16
Bit 09 Bit 08
Bad Data
Almost Full
Bit 01 Bit 00
Pending Pending
Net. Int. 2 Net. Int. 1