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36 PCIE-5565PIORC Reflective Memory Board
PCI Base Address Register 3 contains the starting address for PIO memory
mapped accesses to the Reflective Memory RAM. The value in this register is
loaded by the system BIOS. It depends on both the amount of installed SDRAM
and the settings of S1 switch positions 3 and 4. The address offset range is:
$0 to $01FFFFF for the 2 MByte window setting,
$0 to $0FFFFFF for the 16 MByte window setting,
$0 to $3FFFFFF for the 64 MByte window setting,
$0 to $7FFFFFF for the 128 MByte SDRAM option, and
$0 to $FFFFFFF for the 256 MByte option.
Table 3-14 PCI Base Address Register 3 for Access to Reflective Memory
Bit
Description
0
Memory Space Indicator. Writing zero (0) indicates the register
maps into Memory Space. Writing a one (1) indicates the
register maps into I/O Space.
2:1
Register Location. Values:
00 - Locate anywhere in 32-bit Memory Address Space.
01 - Locate below 1 MByte Memory Address Space.
10 - Locate anywhere in 64-bit Memory Address Space.
11 - Reserved
If I/O Space, Bit 1 is always 0 and Bit 2 is included in the base
address.
3
Prefetchable (If Memory Space).
Writing a one (1) indicates there are no side effects on reads.
Does not affect operation of the Reflective Memory. The
associated Bus Region Descriptor register controls prefetching
functions of this address space. If I/O Space, Bit 3 is included in
the base address.
31:4
Memory Base Address. Memory Base Address for access to
SDRAM.
*NOTE: This register will be altered by the system BIOS during the system boot process.
Table 3-15 PCI Base Address Register 4
Bit
Description
31:0
Reserved.
Table 3-16 PCI Base Address Register 5
Bit
Description
31:0
Reserved.
PCIBAR3: Offset $1C
Read
Yes
Yes
Yes
Yes
PCIBAR4: Offset $20
Read
Yes
PCIBAR5: Offset $24
Read
Yes
*Value after
Write
PCI Reset
No
0
Mem: No I/O
00
Bit 1 no,
Bit 2 yes
Mem: No
0
I/O: Yes
Yes
$0
Value after
Write
PCI Reset
No
$0
Value after
Write
PCI Reset
No
$0
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