Table 3-31 Device Status Register Bit Definition; Table 3-32 Link Capabilities Register Bit Definition; Table 3-33 Link Control Register Bit Definition - GE PCIE-5565PIORC* Hardware Reference Manual

Table 3-31 Device Status Register Bit Definition

Bit(s) Field
15:6 Reserved
5 Transactions Pending When set to one, indicates that this function
4 Aux Power Detected
3 Unsupported Request
Detected
2 Fatal Error Detected
1 Non-Fatal Error
Detected
0 Correctable Error
Detected

Table 3-32 Link Capabilities Register Bit Definition

Bit(s) Field
31:24 Port Number
23:18 Reserved
17:15 L1 Exit Latency
14:12 L0s Exit Latency
11:10 Active Stake Link PM
Support
9:4 Maximum Link Width
3:0 Maximum Speed

Table 3-33 Link Control Register Bit Definition

Bit(s) Field
15:8 Reserved
7 Extended Sync
6 Common Clock
Configuration
5 Retrain link
4 Link Disable
3 Read Completion
Boundary Control
2 Reserved
1:0 Active State PM
Control
Device Status Register Bit Definition: Offset 0x08A
Description
has issued non-posted request packets
which have not yet been completed.
Aux power not required. Hardwired to 0
1 = Error Detected
0 = Error Not Detected
1 = Error Detected
0 = Error Not Detected
1 = Error Detected
0 = Error Not Detected
1 = Error Detected
0 = Error Not Detected
Link Capabilities Register Bit Definition: Offset 0x08C
Description
Hardwired to 0x01
Hardwired to 000000
More than 64 micro seconds. Hardwired to 111 R
More than 4 micro seconds. Hardwired to 111
L0s entry supported. Hardwired to 01
X4. Hardwired to 000100
2.5 Gb/s Hardwired to 0001
Link Control Register Bit Definition: Offset 0x090
Description
Hardwired to 000
1 = 4096 FTS Ordered Sets during L0s state and 1024
TS1 Ordered Sets prior to entering the recovery state
0 = Do not use extended FTS and TS1 ordered sets
1 = Uses common clock on both ends of link
0 = Uses separate clocks on each end of link
1 = Retrain Link
0 = Do not Retrain Link
1 = Disable Link
0 = Do not Disable Link
0 = 64 Byte
1 = 128 Byte
00 = Disabled
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled
R/W
R
R
R
RW1C
RW1C
RW1C
RW1C
R/W
R
R
R
R
R
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Programming 41