Table 3-30 Device Control Register Bit Definition - GE PCIE-5565PIORC* Hardware Reference Manual

40 PCIE-5565PIORC Reflective Memory Board
Table 3-29 Device Capabilities Register Bit Definition (Continued)
4:3 Phantom Functions
Supported
2:0 Max Payload Size
Supported

Table 3-30 Device Control Register Bit Definition

Bit(s) Field
15 Reserved
14:12 Max Read Request
11 Enable No Snoop
10 Aux Power PM Enable Not Supported. Hardwired to 0
9 Phantom Functions
Enable
8 Extended Tag Field
Enable
7:5 Max payload Size
4 Enable Relaxed
Ordering
3 Unsupported Request
Reporting Enable
2 Fatal Error Reporting
Enable
1 Non-Fatal Error
Reporting Enable
0 Correctable Error
Reporting Enable
Device Capabilities Register Bit Definition: Offset 0x084
Not Supported. Hardwired to 00
Max payload is 256 bytes
001
Device Control Register Bit Definition: Offset 0x088
Description
This card will only generate a max read
request of 128 bytes, but this register may
be written to any of the following.
- 000 = 128 Byte
- 001 = 256 Byte
- 010 = 512 Byte
- 011 = 1K Byte
-100 = 2K Byte
-101 = 4K Byte
1 = Enable
0 = Disable
Not Supported. Hardwired to 0
Not Supported. Hardwired to 0
000 = 128 Byte
001 = 256 Byte
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
R
R
R/W
R
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W