Table 3-26 Power Management Capability Structure; Table 3-27 Pcie Capability Structure; Table 3-28 Pcie Capabilities Register Bit Definition; Table 3-29 Device Capabilities Register Bit Definition - GE PCIE-5565PIORC* Hardware Reference Manual

Table 3-26 Power Management Capability Structure

Offset 31::24
0x078 Capabilities Register (Hardwire to 0x0003)
0x070 Data (hardwired to 0x00)

Table 3-27 PCIe Capability Structure

Offset 31::24
0x080 PCI Express Capabilities Register
0x084
0x088
0x08C
0x090

Table 3-28 PCIe Capabilities Register Bit Definition

Bit(s) Field
15:14 Reserved
13:9 Interrupt Message
Number
8 Slot Implemented
7:4 Device/Port type
3:0 Capability Version

Table 3-29 Device Capabilities Register Bit Definition

Bit(s) Field
31:28 Reserved
27:26 Captured Slot Power
Limit Scale
25:18 Capture Slot Power
Limit Value
17:15 Reserved
14 Power Indicator
Present
13 Attention Indicator
Present
12 Attention Indicator
Button Present
11:9 Endpoint L1
Acceptable Latency
8:6 Endpoint L0
Acceptable Latency
5 Extended TAG Field
Supported
23::16
PM Control/Status Bridge
Extensions (hardwired to
0xx00)
23::16
Device Capabilities
Device Status
Link Capabilities
Link Status
PCIe Capabilities Register Bit Definition: Offset 0x082
Description
Not Supported. Hardwired to 0
Not Supported. Hardwired to 0
Indicates the PCIe logical device type.
- 0001:Legacy PCI Express Endpoint
- 0x1
Device Capabilities Register Bit Definition: Offset 0x084
Description
Not Applicable to endpoint. Hardwired to 00 R
Not applicable to endpoint. Hardwired to
00011001
- 001
Not Supported. Hardwired to 0
Not Supported. Hardwired to 0
Not Supported. Hardwired to 0
000 (less than 1 micro seconds)
000 (less than 64 nano seconds)
5-bit Tag field supported
0
15:8 7:0
0x80 Next Cap Ptr 0x01 Capability ID
Power Management Status and Control
(hardwired to 0x0008)
15:8 7:0
0x00 0x10 Capability ID
Device Control
Link Control
R/W
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
R
Programming 39