Table 3-10 Pci Built-In Self Test Register; Table 3-11 Pci Base Address Register 0 For Access To Local Configuration Registers - GE PCIE-5565PIORC* Hardware Reference Manual

34 PCIE-5565PIORC Reflective Memory Board

Table 3-10 PCI Built-in Self Test Register

Bit Description
3:0 BIST Pass/Failed.
Writing $0 indicates a device passed its test.
Non-$0 values indicate a device failed its test. Device-specific
failure codes can be encoded in a non-$0 value.
5:4 Reserved.
6 PCI BIST Interrupt Enable. The PCI bus writes a one (1) to
enable BIST, which generates an interrupt to the Local bus. The
Local bus resets this bit when BIST is complete. The software
should fail device if BIST is not complete after two seconds.
Refer to the Runtime registers for interrupt Control and Status.
7 BIST Support.
Returns a one (1) if device supports BIST.
Returns a zero (0) if device is not BIST-compatible.
PCI Base Address Register 0 contains the starting address for memory mapped
accesses to the Local Configuration Registers, which include the interrupt Control
and Status and the DMA Registers. The value in this register is loaded by the
system BIOS.

Table 3-11 PCI Base Address Register 0 for Access to Local Configuration Registers

Bit Description
0 Memory Space Indicator.
Writing zero (0) indicates the register maps into Memory Space.
Writing a one (1) indicates the register maps into I/O Space.
(NOTE: Hardcoded to zero (0).)
2:1 Register Location. Values:
00 - Locate anywhere in 32-bit Memory Address Space.
01 - Locate below 1 MByte Memory Address Space.
10 - Locate anywhere in 64-bit Memory Address Space.
11 - Reserved
(NOTE: Hardcoded to 00.)
3 Prefetchable. Writing a one (1) indicates there are no side
effects on reads. (NOTE: Hardcoded to zero (0).)
8:4 Memory Base Address. Memory Base Address for access to
Local Configuration registers (requires 512 bytes).
(NOTE: Hardcoded to $0.)
31:9 Memory Base Address. Memory Base Address for access to
Local Configuration registers.
*NOTE: This register will be altered by the system BIOS during the system boot process.
PCI Built-in Self Test: Offset $0F
PCIBAR0: Offset $10
Value after
Read Write
PCI Reset
Yes No $0
Yes No 00
Yes Yes 0
Yes No 0
*Value after
Read Write
PCI Reset
Yes No 0
Yes No 00
Yes No 0
Yes No $0
Yes Yes $0