Table 3-4 Pci Status Register; Table 3-5 Pci Revision Id Register - GE PCIE-5565PIORC* Hardware Reference Manual

Ultrahigh speed fiber-optic reflective memory with interrupts
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32 PCIE-5565PIORC Reflective Memory Board

Table 3-4 PCI Status Register

Bit
Description
2:0
Reserved
3
Interrupt Status.
Set by the Reflective Memory when the function would normally
assert an interrupt pin, regardless of interrupt disable bit state.
4
New Capabilities Functions Support.
Hardwired to a one (1). The Reflective Memory implements a
capabilities list.
5
66 MHz Capable.
Not applicable to PCI Express.
6
User Definable Functions.
If set to one (1), this device supports user definable functions.
Read-only from the PCI bus.
7
Fast Back-to-Back Capable.
Not applicable to PCI Express.
8
Master Data Parity Error Detected.
Set by the Reflective Memory acting as a master when it detects
a poisoned completion, if parity error response bit is set.
10:9
DEVSEL# Timing.
Not applicable to PCI Express.
11
Target Abort.
When set to one (1), indicates the Reflective Memory has
signaled a Completer Abort.
Writing a one (1) clears this bit to zero (0).
12
Received Target Abort.
When set to one (1), indicates the Reflective Memory has
received a Completer Abort.
Writing a one (1) clears this bit to zero (0).
13
Received Master Abort.
When set to one (1), indicates the Reflective Memory has
received a Unsupported Request Completion Status.
Writing a one (1) clears this bit to zero (0).
14
Signal System Error.
When set to one (1), indicates the Reflective Memory has sent
an ERR_FATAL or ERR_NONFATAL message.
Writing a one (1) clears this bit to zero (0).
15
Detected Parity Error.
When set to one (1), indicates the Reflective Memory has
detected a poisoned completion, even if parity error handling is
disabled (the Parity Error Response bit in the Command register
is clear).
Writing a one (1) clears this bit to zero (0)

Table 3-5 PCI Revision ID Register

Bit
Description
7:0
Revision ID. Revision of board Yes
PCI Status: Offset $06
PCI Revision ID: Offset $08
Read
Write
No
Value after
Read
Write
PCI Reset
Yes
No
$0
Yes
No
0
Yes
No
1
Yes
No
0
Yes
No
0
Yes
No
0
Yes
Yes/Clr
0
Yes
No
0
Yes
Yes/Clr
0
Yes
Yes/Clr
0
Yes
Yes/Clr
0
Yes
Yes/Clr
0
Yes
Yes/Clr
0
Value after
PCI Reset
Current Rev#

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