GE PCIE-5565PIORC* Hardware Reference Manual page 63

63 PCIE-5565PIORC Reflective Memory Board
DMA channel 0 mode setting:
Bit 9 set to 1 indicates the use of Scatter‐
Gather DMA (not normal Block mode).
DMA channel 0 PCI starting address:
This register is unused during Scatter‐
Gather DMA.
DMA channel 0 local starting address:
Set to the starting address of the local
(RFM) memory (for either source or
destination transfers).
NOTE: The first local (RFM) memory
location is at $0.
DMA channel 0 transfer size:
Set to the total number of bytes to be
transferred in all blocks (maximum
$7FFFFF).
DMA channel 0 Descriptor Pointer:
Set bits 31:4 to the PCI Address of the first
DMA Scatter‐Gather descriptor location.
Set bit‐3 to 0 for PCI‐to‐Local
or set bit‐3 to 1 for Local‐to‐PCI.
DMA channel 0 PCI DAC upper address:
This register is unused during Scatter‐
Gather DMA.
3. To initiate and monitor the transfer, access DMACSR0 as follows:
DMA channel 0 Command/Status register:
DMACSR0 at PCIBAR0 + offset $A8.
Write $0003 to start the transfer, then poll the same register.
When Bit 4 is high (1), the DMA cycle is complete.
NOTE
Polling read cycles take priority over the DMA cycles. Overly aggressive polling will slow the DMA
transfer. Rather than polling for the DMA done condition, the user can choose to enable the PCI
interrupt on DMA done by setting Bit 18 of the INTCSR at offset $68 to high (1). Once the interrupt is
enabled, the user software routine waits for the interrupt to occur.
4. After the DMA is finished, clear the DMA completion bit with a write to
DMACSR0 as follows. This is necessary when using DMA interrupts.
DMA channel 0 Command/Status register:
DMACSR0 at PCIBAR0 + offset $A8.
Write $8 to clear the DMA completion bit before attempting
another DMA.
DMAMODE0 at PCIBAR0 + offset $80
DMAPADR0 at PCIBAR0 + offset $84
DMALADR0 at PCIBAR0 + offset $88
DMASIZ0 at PCIBAR0 + offset $8C
DMADPR0 at PCIBAR0 + offset $90
DMADAC0 at PCIBAR0 + offset $B4