Table 3-36 Mode/Dma Arbitration Register; Table 3-37 Big/Little Endian Descriptor Register - GE PCIE-5565PIORC* Hardware Reference Manual

44 PCIE-5565PIORC Reflective Memory Board

Table 3-36 Mode/DMA Arbitration Register

Bit Description
23:0 Reserved
24 Reserved
25 Reserved
31:26 Reserved

Table 3-37 Big/Little Endian Descriptor Register

Bit Description
4:0 Reserved
5 PCI PIO RFM Address Space Big Endian Mode (Address Invariance).
Writing a one (1) specifies use of Big Endian data ordering for PCI
accesses to the RFM Address Space.
Writing a zero (0) specifies Little Endian ordering.
6 Reserved
7 DMA Channel 0 Big Endian Mode (Address Invariance).
Writing a one (1) specifies use of Big Endian data ordering for DMA
Channel 0 accesses to the RFM Address Space.
Writing a zero (0) specifies Little Endian ordering.
MARBR: BAR0/1 Offset $08 or $AC
BIGEND: BAR0/1 Offset $0C
Value after
Read Write
PCI Reset
Yes No $040000
Yes Yes 0
Yes No 1
Yes No $00
Value after
Read Write
PCI Reset
Yes No $00
Yes Yes 0
Yes No 0
Yes Yes 0