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Bits 15 through 08: Reserved – These bits are reserved.
Bit 07:
TX FIFO Empty – A logic high (1) indicates the TX FIFO is
currently empty. This bit provides immediate status only (not
latched) and is read‐only.
Bit 06:
TX FIFO Almost Full – A logic high (1) indicates the TX FIFO
is currently almost full. This bit provides immediate status
only (not latched) and is read‐only. Periodic assertion of this
bit is normal.
Bit 05:
Latched RX FIFO Full – A logic high (1) indicates the RX
FIFO has experienced a full condition at least once. This bit is
read‐only within this register. To clear this condition write to
the corresponding bit within the Local Interrupt Status
Register.
NOTE
The occurrence of the Latched RX FIFO Full signal is a fault condition due to a board malfunction
and indicates that the received data may have been lost.
Bit 04:
Latched RX FIFO Almost Full – A logic high (1) indicates the
RX FIFO is operating at the maximum acceptable rate. Under
normal operating conditions, this event should not occur.
This bit is read‐only within this register. To clear this
condition, write to the corresponding bit within the Local
Interrupt Status Register.
Bit 03:
Latched Sync Loss – A logic high (1) indicates the receiver
circuitry has detected the loss of a valid signal at least once
since the last time the flag has been cleared. Under normal
operating conditions, this event should not occur and may
indicate a loss of data. A logic high may indicate the
receiver's link was intentionally or unintentionally
disconnected.
Bit 02:
RX Signal Detect – A logic high (1) indicates the board
receiver is currently detecting light. This bit provides
immediate status only (not latched) and is read‐only.
Bit 01:
Bad Data – A logic high (1) indicates the board receiver
circuit has detected bad (invalid) data at least once since
power up or since the flag had previously been cleared.
Under normal operating conditions, this event should not
occur and may indicate a loss of data. This bit is read‐only
within this register. To clear this condition, write to the
corresponding bit within the Local Interrupt Status Register.
Bit 00:
Own Data – A logic high (1) indicates the board has detected
the return of its own data packet at least once since this bit
has previously been cleared. This bit serves as an indicator
that the link is intact. The Own Data bit should be set any
time a write to the onboard memory occurs or any time
network interrupt is initiated. This bit is both read and write
accessible.
Programming 53
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