Pci Configuration Registers; Table 3-1 Pci Configuration Registers; Table 3-2 Pci Configuration Id Registers - GE PCIE-5565PIORC* Hardware Reference Manual

3.1 PCI Configuration Registers

30 PCIE-5565PIORC Reflective Memory Board
The PCI Configuration registers are located in 256 bytes of the PCI Configuration
Space, which follows a template defined by the PCI Specification v2.2. The first
64 bytes of the PCI Configuration Space are composed of a fully predefined
header. Within that header region, each device implements only the necessary
and relevant registers. However, all registers and bit functions within the header
region, that are present, must comply with the definitions of the PCI Specification.
Beyond the first 64 byte boundary, each device can implement additional device
unique registers. Although the PCI Configuration registers are accessible at all
times, they are rarely altered by the user.

Table 3-1 PCI Configuration Registers

Address (Hex) 31..24
00 Device ID
04 Status Register
08
0C BIST
10
14
18
1C
20
24
28
2C Subsystem Device ID
30
34
38
3C 0x00
50..5C
78..7C Power Management Capability Structure
80..90
NOTE
All registers can be accessed as either Byte, Word or Double-word request.

Table 3-2 PCI Configuration ID Registers

Bit Description
15:0 Vendor ID.
Identifies manufacturer of device.
31:16 Device ID.
Identifies particular device.
23..16 15..8
Vendor ID
Command Register
Class Code
Header Type Latency Timer
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Cardbus CIS Pointer
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Reserved
0x00 Interrupt Pin
MSI Capability Structure
PCIe Capability Structure
PCI Configuration ID: Offset $00
7..0
Revision ID
Cache Line Size
CAP. Pointer
Interrupt Line
Read Write
Yes No
Yes No
Value after
PCI Reset
$114A
$5565