Local Configuration Registers; Table 3-35 Local Configuration And Dma Control Registers - GE PCIE-5565PIORC* Hardware Reference Manual

3.2 Local Configuration Registers

The Local Configuration Registers are memory cycle accessible at the offsets from
the value stored in Base Address Register 0. The registers at offsets $00 to $FF are
also I/O cycle accessible at the offsets from the value stored in Base Address
Register 1. The offsets are specified below.

Table 3-35 Local Configuration and DMA Control Registers

PCI
(Offset from Register Name
Base Address)
$00-$07 Reserved
$08 MARBR (same as $AC)
$0C Big/Little Endian Descriptor
$10-$67 Reserved
$68 INTCSR
$70 Reserved
$74 PCI H Rev
$78 Reserved
$80 DMA Channel 0 Mode
$84 DMA Channel 0 PCI Address
$88 DMA Channel 0 Local Address
$8C DMA Channel 0 Transfer Byte Count
$90 DMA Channel 0 Descriptor Pointer
$94-$A7 Reserved
$A8 DMA CSR 0
$AC MARBR (same as $08)
$B0 Reserved
$B4 DMA Channel 0 PCI DAC Upper Address
$B8-$EF Reserved
$F0 PCI PIO Address Range
$F4 PCI PIO Base Address (Remap)
$F8-$1FF Reserved
NOTE
To ensure software compatibility with other RFM-5565 boards using the PLX 9656 and to ensure
compatibility with future enhancements, write zero (0) to all unused bits.
Writable
N/A
Y
Y
N/A
Y
N/A
Y
N/A
Y
Y
Y
Y
Y
N/A
Y
Y
N/A
Y
N/A
N
Y
N/A
Programming 43