Table 3-45 Dma Channel 0 Transfer Size (Bytes) Register; Table 3-46 Dma Channel 0 Descriptor Pointer Register; Table 3-47 Dma Channel 0 Command/Status Register - GE PCIE-5565PIORC* Hardware Reference Manual

Table 3-45 DMA Channel 0 Transfer Size (Bytes) Register

Bit Description
22:0 DMA Transfer Size (Bytes). Indicates the number of bytes to transfer
during a DMA operation.
31:23 Reserved

Table 3-46 DMA Channel 0 Descriptor Pointer Register

Bit Description
0 DMA Channel 0 Descriptor Location.
A one (1) indicates PCI Address space.
2:1 Reserved
3 Direction of Transfer.
Writing a one (1) indicates transfer from the RFM to the PCI bus.
Writing a zero (0) indicates transfer from the PCI bus to the RFM.
31:4 Channel 0 First Descriptor Address.
This field holds bits [31:4] of the first DMA descriptor address. The first
descriptor address must be aligned on a 16-byte boundary (i.e.,
address bits [3:0] are considered to be $0).

Table 3-47 DMA Channel 0 Command/Status Register

Bit Description
0 Channel 0 Enable.
Writing a one (1) enables channel to transfer data.
Writing a zero (0) disables the channel from starting a DMA
transfer.
1 Channel 0 Start.
Writing a one (1) causes channel to start transferring data if the
channel is enabled.
2 Reserved
3 Channel 0 Clear Interrupt.
Writing a one (1) clears Channel 0 interrupts.
4 Channel 0 Inactive.
Reading a one (1) indicates a channel transfer is complete.
Reading a zero (0) indicates a channel transfer is not complete.
7:5 Reserved
DMASIZ0: BAR0/1 Offset $8C
DMADPR0: BAR0/1 Offset $90
DMACSR0: BAR0/1 Offset $A8
Value after
Read Write
PCI Reset
Yes Yes $0
Yes No $0
Value after
Read Write
PCI Reset
Yes No 1
N/A N/A 0
Yes Yes 0
Yes Yes $0
Value after
Read Write
PCI Reset
Yes Yes 0
No Yes/Set 0
No No 0
No Yes/Clr 0
Yes No 1
Yes No 000
Programming 47