Table 3-3 Pci Command Register - GE PCIE-5565PIORC* Hardware Reference Manual

Table 3-3 PCI Command Register

Bit Description
0 I/O Space.
Writing a one (1) allows the device to respond to I/O Space
accesses.
Writing a zero (0) disables the device from responding to I/O
Space accesses.
1 Memory Space.
Writing a one (1) allows device to respond to Memory Space
accesses.
Writing a zero (0) disables the device from responding to
Memory Space accesses.
2 Master Enable.
Writing a one (1) allows the device to behave as a bus master.
Writing a zero (0) disables the device from generating bus
master accesses.
3 Special Cycle.
Not Supported
4 Reserved
5 VGA Palette Snoop.
Not Supported
6 Parity Error Response.
Writing a zero (0) indicates parity error is ignored and the
operation continues.
Writing a one (1) indicates parity checking is enabled.
7 Wait Cycle Control.
Controls whether a device does address/data stepping.
A zero (0) indicates the device never does stepping.
A one (1) indicates the device always does stepping.
(NOTE: Hardwired to zero (0).)
8 SERR# Enable.
Writing a one (1) enables SERR# driver.
Writing a zero (0) disables SERR# driver.
9 Reserved
10 Interrupt Disable:
When set (1), this bit disables the Reflective Memory from
asserting its interrupt pin.
When not set (0), interrupts are generated normally.
15:11 Reserved
*NOTE: This register will be altered by the system BIOS during the system boot process (e.g., $0107).
PCI Command: Offset $04
Read
Yes
Yes
Yes
Yes
N/A
Yes
Yes
Yes
Yes
N/A
Yes
Yes
*Value after
Write
PCI Reset
Yes 0
Yes 0
Yes 0
No 0
N/A 0
No 0
Yes 0
No 0
Yes 0
N/A 0
Yes 0
No $0
Programming 31