Data Communication Between Cpu Modules - Mitsubishi Electric MELSEC iQ-R Series User Manual

Programmable controller
Hide thumbs Also See for MELSEC iQ-R Series:
Table of Contents

Advertisement

12.2

Data Communication Between CPU Modules

Data can be sent or received between CPU modules in a multiple CPU system.
Buffer memory
The direct access communication enables data writing or reading between CPU modules.
The methods for the data communication are as follows:
Communication
method
Data communication with
CPU buffer memory
Data communication with
fixed scan
communication area
12 BUS ACCESS FUNCTION
112
12.2 Data Communication Between CPU Modules
Buffer memory
Purpose
Use this method when sending or
receiving data at the timing of each
CPU module.
Use this method when sending or
receiving data with adjusting the
timing between CPU modules.
Description
The sending side CPU module writes data to the CPU buffer memory in the host CPU.
The receiving side CPU module reads data from the CPU buffer memory of the send target
CPU module (another CPU module).
For the communication method, refer to the following:
Page 117 Data communication with CPU buffer memory
The sending side CPU module writes data to the fixed scan communication area (send
area) in the host CPU.
The receiving side CPU module reads data from the fixed scan communication area
(receive area) in the CPU module of the send source CPU module.

Advertisement

Table of Contents
loading

This manual is also suitable for:

Melsec iq-r melsecwincpu

Table of Contents