Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 8
Characterization kit ibert
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Also See for Virtex-7 FPGA VC7222:
- Getting started manual (68 pages) ,
- User manual (65 pages) ,
- Getting started manual (44 pages)
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The ZIP file contains these files:
•
BIT files
vc7222_ibert_q113_325.bit
vc7222_ibert_q114_325.bit
vc7222_ibert_q115_325.bit
vc7222_ibert_q213_325.bit
vc7222_ibert_q214_325.bit
vc7222_ibert_q215_325.bit
vc7222_ibert_q300_225.bit
vc7222_uarttest.bit
•
Probe files
vc7222_ibert_q113_debug_nets.ltx
vc7222_ibert_q114_debug_nets.ltx
vc7222_ibert_q115_debug_nets.ltx
vc7222_ibert_q213_debug_nets.ltx
vc7222_ibert_q214_debug_nets.ltx
vc7222_ibert_q215_debug_nets.ltx
vc7222_ibert_q300_debug_nets.ltx
•
Tcl scripts
add_scm2.tcl
setup_scm2_325_00_GTH.tcl
setup_scm2_225_00_GTZ.tcl
The Tcl scripts are used to help merge the IBERT and SuperClock-2 source code (described
in
Chapter 2, Creating the GTH IBERT Core
and to set up the SuperClock-2 module (described in
page 20
in the GTH section and
section).
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Chapter 1: VC7222 IBERT Getting Started Guide
and in
Chapter 3, Creating the GTZ IBERT
Starting the SuperClock-2 Module,
Starting the SuperClock-2 Module, page 36
www.xilinx.com
Core)
in the GTZ
8
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