Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 11

The SuperClock-2 module provides LVDS clock outputs for the GTH transceiver reference
clock in the IBERT demonstration.
SMA connections on the clock module which can be connected to the reference clock
cables.
The image in
Note:
board.
X-Ref Target - Figure 1-3
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
The Si570 oscillator does not support LVDS output on Rev. B and earlier revisions of the
Note:
SuperClock-2 module.
For the GTH IBERT demonstration, the output clock frequencies are preset to 325.00 MHz.
For more information regarding the SuperClock-2 module, see the HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770)
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Figure 1-3
Figure 1-3 is for reference only and might not reflect the current revision of the
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
www.xilinx.com
Chapter 1: VC7222 IBERT Getting Started Guide
shows the location of the differential clock
[Ref 2].
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