Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 61

2. A Customize IP window opens. In the Design Options tab, set the system clock
frequency to 200 MHz, the input Standard to LVDS, the P and N Pin location to AL24
and AL25, respectively
X-Ref Target - Figure 3-2
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
(Figure 3-2).
Figure 3-2: Customize IP - Design Options
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Chapter 3: Creating the GTZ IBERT Core
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