Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 36

Starting the SuperClock-2 Module
The IBERT demonstration designs use an integrated VIO core to control the clocks on the
SuperClock-2 module. The SuperClock-2 module features two clock-source components:
• An always-on Si570 crystal oscillator
• An Si5368 jitter-attenuating clock multiplier
Outputs from either source can be used to drive the transceiver reference clocks.
To start the SuperClock-2 module:
1. The Vivado Design Suite Hardware window shows the System ACE SD Controller and the
XC7VH580T devices. The XC7VH580T device is reported as programmed. In the
Hardware Device Properties window, enter the file path to the Q300 Probes file
(vc7222_ibert_q300_debug_nets.ltx) in the extracted IBERT files from the SD
card (Figure
X-Ref Target - Figure 1-27
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
1-27).
Figure 1-27: Adding the Probes File
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Chapter 1: VC7222 IBERT Getting Started Guide
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