Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 27

In Case of RX Bit Errors
If there are initial bit errors after linking, or as a result of changing the TX or RX pattern, click
the respective BERT Reset button to zero the count.
If the MGT Link Status shows No Link for one or more transceivers:
• Make sure the blue elastomer seal is connected to the bottom of the BullsEye cable and
the cable is firmly connected and flush on the board.
• Increase the TX differential swing of the transceiver (to compensate for any loss due to
PCB process variation).
• Click the respective TX Reset button followed by BERT Reset.
Additional information on the Vivado Design Suite software and IBERT core can be found in
Vivado Design Suite User Guide: Programming and Debugging (UG908)
IP Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTH Transceivers Product Guide for
Vivado Design Suite (PG152)
Closing the IBERT Demonstration
To stop the IBERT demonstration:
1. Close the Vivado Design Suite application by selecting File > Exit.
2. Place the main power switch SW1 in the off position.
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Chapter 1: VC7222 IBERT Getting Started Guide
[Ref 4].
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[Ref 3] and LogiCORE
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