Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 54

12. The SuperClock-2 source code now needs to be added to the example IBERT wrapper. In
the Sources window, double-click example_ibert_7series_gth_0 in the Design Sources
folder to open the verilog code. Add the top level ports from top_scm2.v to the
module declaration, and instantiate the top_scm2 module in the example ibert wrapper
(Figure 2-10). Click File > Save File.
X-Ref Target - Figure 2-10
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Figure 2-10: SuperClock-2 in the Example IBERT Wrapper
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Chapter 2: Creating the GTH IBERT Core
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