Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 67

7. In the Sources window, Design Sources should now reflect that the SuperClock-2
module is part of the example IBERT design
X-Ref Target - Figure 3-8
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Figure 3-8: Design Sources File Hierarchy
www.xilinx.com
Chapter 3: Creating the GTZ IBERT Core
(Figure 3-8).
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