Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 47

Characterization kit ibert
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5. In the Manage IP Settings window, select Verilog for Target language, Vivado
Simulator for Target simulator, Mixed for Simulator language, and a directory to save
the customized IP
Make sure the directory name does not include spaces.
Note:
X-Ref Target - Figure 2-3
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
(Figure
2-3). Click Finish.
Figure 2-3: Manage IP Settings
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Chapter 2: Creating the GTH IBERT Core
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