Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 35

Setting up the Vivado Design Suite
The procedure to launch the Vivado Suite is detailed in
page 17.
In the Open Hardware Target window it is highly recommended to lower the JTAG clock
frequency to 10 MHz or lower for reliable JTAG communication during the GTZ
demonstration
X-Ref Target - Figure 1-26
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
(Figure 1-26).
Figure 1-26: Select Hardware Target
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Chapter 1: VC7222 IBERT Getting Started Guide
Setting Up the Vivado Design Suite,
35
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