Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 10

Figure 1-1
Note:
All GTH transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with the Samtec BullsEye connector.
pad, and Figure 1-2
X-Ref Target - Figure 1-2
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
is for reference only and might not reflect the current revision of the board.
B shows the connector pinout.
Figure 1-2: A – GTH Connector Pad. B – GTH Connector Pinout
www.xilinx.com
Chapter 1: VC7222 IBERT Getting Started Guide
Figure 1-2 A shows the connector
10
Send Feedback