Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 51

9. In the Clock Settings tab, select DIFF SSTL15 for the I/O Standard, enter AL24 for P
Package Pin and AL25 for N Package Pin (the FPGA pins that the system clock connects
to), and ensure the Frequency is set to 200.00
the next window to generate the output products.
X-Ref Target - Figure 2-7
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Figure 2-7: Customize IP - Clock Settings
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Chapter 2: Creating the GTH IBERT Core
(Figure 2-7). Click OK. Click Generate in
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