Xilinx Virtex-4 Configuration User Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Motherboard
  5. Virtex-4 RocketIO
  6. Configuration user manual

Xilinx Virtex-4 Configuration User Manual

Fpga
Hide thumbs Also See for Virtex-4:
Table of Contents

Advertisement

Quick Links

Download this manual See also: User Manual
Virtex-4 FPGA
Configuration
User Guide
UG071 (v1.12) June 2, 2017
R

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Virtex-4 and is the answer not in the manual?

Questions and answers

Related Manuals for Xilinx Virtex-4

Summary of Contents for Xilinx Virtex-4

  • Page 1 Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 2: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
  • Page 3 Version Revision 01/19/06 Completed grammatical and style edits for clarity and compliance to Xilinx documentation standards. Added preface, not included in previous versions. Corrected Table 1-1, page 13 (Note 2.). Added “HSWPEN has a weak pull-up prior to and during configuration” to...
  • Page 4 Version Revision 06/02/17 1.12 Chapter 8: • Added note after first paragraph to clarify that configuration memory readback is not supported for flight applications in Virtex-4QV devices. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 5: Table Of Contents

    ....... . . 39 PROM Files for Ganged Serial Configuration Virtex-4 FPGA Configuration User Guide www.xilinx.com...
  • Page 6 Using Boundary-Scan in Virtex-4 Devices ........
  • Page 7 ............113 Virtex-4 FPGA Configuration User Guide www.xilinx.com...
  • Page 8 Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 9: Preface: About This Guide

    Preface About This Guide This document describes the Virtex®-4 Configuration. Complete and up-to-date documentation of the Virtex-4 family of FPGAs is available on the Xilinx web site at http://www.xilinx.com/products/virtex4/index.htm. Guide Contents • Chapter 1, “Configuration Overview” • Chapter 2, “Configuration Interfaces”...

  • Page 10: Additional Resources

    • Virtex-4 FPGA PCB Designers Guide This designer’s guide provides information on the design of PCBs for Virtex-4 devices. It considers all aspects of the PCB from the system level down to the minute details. This guide focuses on strategies for making design decisions at the PCB and interface level.

  • Page 11: Online Document

    Cross-reference link to a Red text See the Virtex-4 User Guide. location in another document Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...
  • Page 12 Preface: About This Guide www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 13: Chapter 1: Configuration Overview

    Introduction Virtex®-4 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx® FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes: •...
  • Page 14 Configuration Overview The terms Master and Slave refer to the direction of the configuration clock (CCLK): • In Master configuration modes, the Virtex-4 device drives the configuration clock (CCLK) from an internal oscillator • In Slave configuration modes, the configuration clock is an input.

  • Page 15: Setup (Steps 1-3)

    Bitstream Loading Start Finish ug071_02_122105 Figure 1-2: Device Power-Up (Step 1) For configuration, Virtex-4 devices require power on the V , and CC_CONFIG CCAUX pins. There are no power-supply sequencing requirements. CCINT All JTAG and serial configuration pins are located in a separate, dedicated bank with a dedicated V ) supply.

  • Page 16: Clear Configuration Memory (Step 2, Initialization)

    Sheet. Table 41 of the Virtex-4 FPGA Data Sheet shows the configuration power-up timing parameters. Table 7-1 shows the number of frames per Virtex-4 device. Table 1-3: Power Supplies Required for Configuration Pin Name Description Internal core voltage relative to GND.

  • Page 17: Sample Mode Pins (Step 3)

    Serial Modes or the D0–D7 pins for SelectMAP modes on rising configuration clock signals). Delaying Configuration There are two ways to delay configuration for Virtex-4 devices: • The first is to hold the INIT_B pin Low during initialization (Figure 1-3).

  • Page 18: Bitstream Loading (Steps 4-7)

    Figure 1-6: Synchronization (Step 4) Before the configuration data frames can be loaded, a special 32-bit synchronization word (0xAA995566) must be sent to the configuration logic. The synchronization word alerts www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 19: Check Device Id (Step 5)

    Any data on the configuration input pins prior to synchronization is ignored. Synchronization is transparent to most users because all configuration bitstreams (.bit files) generated by the Xilinx ISE® Bitstream Generator (BitGen) software include the synchronization word. Table 1-5 shows signals relating to synchronization.

  • Page 20: Load Configuration Data Frames (Step 6)

    Virtex-4 device ID specified in the bitstream status register. and the actual device ID. Notes: 1. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the JTAG capture sequence is available in Table 8-4.

  • Page 21: Startup (Step 8)

    (see “SelectMAP Configuration Interface” in Chapter Virtex-4 devices use a 32-bit CRC check. The CRC check is designed to catch errors in transmitting the configuration bitstream. There is a scenario where errors in transmitting the configuration bitstream can be missed by the CRC check: Certain clocking errors, such as double-clocking, can cause loss of synchronization between the 32-bit bitstream packets and the configuration logic.
  • Page 22 LOCK_WAIT option is used on a DCM and the LockCycle option is used when the bitstream is generated. Notes: 1. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the JTAG capture sequence is available in Table 8-4.

  • Page 23: Bitstream Encryption

    AES decryption logic is not available to the user design and cannot be used to decrypt any data other than the configuration bitstream. Virtex-4 devices store the encryption key internally in dedicated RAM, backed up by a small externally connected battery. The encryption key can only be programmed onto the device through the JTAG interface;...

  • Page 24: Creating An Encrypted Bitstream

    The encryption key can only be programmed onto a Virtex-4 device through the JTAG interface. The iMPACT tool, provided with the Xilinx ISE software, can accept the .nky file as an input and program the device with the key through JTAG, using a supported Xilinx programming cable.

  • Page 25: Bitstream Encryption And Internal Configuration Access Port (Icap)

    Unless the designer wires the ICAP interface to user I/O, this does not offer attackers a method for defeating the Virtex-4 AES encryption scheme. ICAP is not supported with an encrypted bitstream in the LX, SX, and FX12 devices.
  • Page 26 Chapter 1: Configuration Overview www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 27: Chapter 2: Configuration Interfaces

    In Master serial mode, CCLK is an output. • In Slave serial mode, CCLK is an input. Figure 2-1 shows the basic Virtex-4 serial configuration interface. There are four methods of configuring an FPGA in serial mode: • Master serial configuration •...
  • Page 28 DOUT D_IN INIT_B PROGRAM_B DONE CCLK ug071_14_073007 Figure 2-1: Virtex-4 Serial Configuration Interface Table 2-2 describes the Serial Configuration Interface. Table 2-2: Virtex-4 Serial Configuration Interface Pins Dedicated Pin Name Type or Dual- Description Purpose M[2:0] Input Dedicated Mode Pins – determine configuration mode.

  • Page 29: Clocking Serial Configuration Data

    Serial Configuration Interface Clocking Serial Configuration Data Figure 2-2 shows how configuration data are clocked into Virtex-4 devices in Slave serial and Master serial modes. PROGRAM_B INIT_B Master CLK Begins Here CCLK Master DIN BIT 0 BIT 1 BIT n...

  • Page 30: Slave Serial Configuration

    ± 50%, select a maximum frequency not to exceed the F of the configuration device. The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial PROMs can be cascaded to increase the overall configuration storage capacity.
  • Page 31 ± 50%, select a maximum frequency not to exceed the F of the configuration device. The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial PROMs can be cascaded to increase the overall configuration storage capacity.

  • Page 32: Configuring A Serial Daisy Chain With A Microprocessor Or Cpld

    Configuring a Serial Daisy Chain with a Microprocessor or CPLD If a microprocessor or CPLD is driving configuration instead of a Xilinx serial PROM, all devices in the serial daisy chain can be set for Slave serial configuration mode, or the lead...

  • Page 33: Mixed Serial Daisy Chains

    Virtex-II, Virtex-II Pro, and Spartan-3 families. There are three important design considerations when designing a mixed serial daisy chain: • Many older devices cannot accept as fast a CCLK frequency as a Virtex-4 device can generate. Select a configuration CCLK speed supported by all devices in the chain. •...
  • Page 34 Development System Reference Guide for software settings.) Board Layout for Configuration Clock (CCLK) The Virtex-4 output standard for all configuration I/Os, including CCLK, is different from previous Xilinx FPGAs. To improve performance, the Virtex-4 configuration I/Os use the LVCMOS fast slew rate standard of 12 mA. This change results in faster edge rates to support higher configuration frequencies.
  • Page 35 2 x Z CCLK CCLK CCLK Input 1 Input 2 Input 3 (100 Ω) 2 x Z ug071_2_08_072505 Figure 2-8: Multi-Drop: One CCLK Output, More Than Two CCLK Inputs Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...
  • Page 36 Spartan-II, 4000, etc.). In general, newer devices should appear upstream of older devices. For example, a daisy chain consisting of a Virtex-4, a Virtex-II, a Virtex, and a 4000E device should be arranged with the Virtex-4 device first in the chain, the Virtex-II device second, the Virtex device third, and the 4000E device last.

  • Page 37: Ganged Serial Configuration

    Serial Configuration Interface Maximum CCLK Rate Varies Between Xilinx Device Families Older Xilinx device families require slower CCLK rates than Virtex-4 devices. For mixed serial daisy chains, ensure the Master device does not toggle CCLK faster than the slowest device can tolerate.

  • Page 38: Startup Sequencing (Gts)

    Configuration Interfaces The BitGen startup clock setting must be set for CCLK for serial configuration. The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial PROMs can be cascaded to increase the overall configuration storage capacity.

  • Page 39: Prom Files For Ganged Serial Configuration

    The SelectMAP configuration interface (Figure 2-11) provides an 8-bit bidirectional data-bus interface to the Virtex-4 configuration logic that can be used for both configuration and readback. (For details, refer to Chapter CCLK is an output in Master SelectMAP mode; in Slave SelectMAP, CCLK is an input. One or more Virtex-4 devices can be configured through the SelectMAP bus.
  • Page 40 Chapter 2: Configuration Interfaces Table 2-4: Virtex-4 SelectMAP Configuration Interface Pins (Continued) Dedicated Pin Name Type or Dual- Description Purpose Indicates that the device is not ready to send readback data. For Virtex-4 devices, the BUSY Three-State DOUT_BUSY Dedicated signal is only needed for readback; it is not needed...

  • Page 41: Single Device Selectmap Configuration

    On XC17V00 devices, the reset polarity is programmable. RESET should be set for active Low when using an XC17V00 device in this setup. The Xilinx PROM must be set for parallel mode. Note that this mode is not available for all devices.

  • Page 42: Multiple Device Selectmap Configuration

    The CCLK net requires Thevenin parallel termination. See “Board Layout for Configuration Clock (CCLK),” page Multiple Device SelectMAP Configuration Multiple Virtex-4 devices in Slave SelectMAP mode can be connected on a common SelectMAP bus (Figure 2-14). In a SelectMAP bus, the data pins (SelectMAP data, CCLK, RDWR_B, BUSY, PROGRAM_B, DONE, and INIT_B share a common connection between all of the devices.
  • Page 43 SelectMAP Configuration Interface Otherwise, RDWR_B can be tied Low and BUSY can be ignored. Unlike earlier Virtex devices, the BUSY signal never needs to be monitored when configuring Virtex-4 devices. Refer to “Bitstream Loading (Steps 4-7)” in Chapter 1 and to...

  • Page 44: Ganged Selectmap

    The BitGen startup clock setting must be set for CCLK for SelectMAP configuration. The BUSY signal is not used for ganged SelectMAP configuration. The PROM in this diagram represents one or more Xilinx Platform Flash PROMs. Multiple serial PROMs can be cascaded to increase the overall configurations storage capacity.

  • Page 45: Selectmap Data Loading

    On 17V00 devices, the reset polarity is programmable. Reset should be set for active Low when using a 17V00 device in this setup. The Xilinx PROM must be set for parallel mode. This mode is not available for all devices.

  • Page 46: Continuous Selectmap Data Loading

    BUSY is an output from the FPGA indicating when the device is ready to drive readback data. Unlike earlier Virtex devices, Virtex-4 FPGAs never drive the BUSY signal during configuration, even at the maximum configuration frequency with an encrypted bitstream.
  • Page 47 (See “Startup (Step 8)” in Chapter 13. After configuration has finished, the CS_B signal can be deasserted. 14. After the CS_B signal is deasserted, RDWR_B can be deasserted. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 48: Non-Continuous Selectmap Data Loading

    10. Byte loaded on rising CCLK edge. 11. The user deasserts CS_B; byte ignored. 12. Byte loaded on rising CCLK edge. 13. Byte loaded on rising CCLK edge. 14. Byte loaded on rising CCLK edge. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 49: Selectmap Abort

    BUSY goes High if CS_B remains asserted (Low). The FPGA drives the status word onto the data pins if RDWR_B remains set for read control (logic High). The ABORT lasts for four clock cycles and Status is updated. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 50: Readback Abort Sequence Description

    ABORT Status Word During the configuration ABORT sequence, the device drives a status word onto the SelectMAP data pins. The key for that status word is given in Table 2-5. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 51: Resuming Configuration Or Readback After An Abort

    8 or 32 bits as selected by the mode pin settings. Reconfiguration begins when the synchronization word is clocked into the SelectMAP port. The remainder of the operation is identical to configuration as described above. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 52: Selectmap Data Ordering

    For other applications, it can be more convenient for the source configuration data file to be byte-swapped, meaning that the bits in each byte of the data stream are reversed. For these applications, the Xilinx PROM file generation software can generate byte-swapped PROM files (see “Configuration Data...

  • Page 53: Configuration Data Files

    Configuration Data Files Configuration Data Files Xilinx design tools can generate configuration data files in a number of different formats, as described in Table 2-7. BitGen converts the post-PAR .ncd file into a configuration file, or bitstream. The bitstream contains commands to the FPGA configuration logic as well as configuration data.

  • Page 54: Generating Prom Files

    PROMGen (or iMPACT) when generating a PROM file from multiple bitstreams. To generate the PROM file, specify multiple bitstreams using the PROMGen -n option or the iMPACT File Generation Wizard. Refer to software documentation for details. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 55: Prom Files For Selectmap Configuration

    PROM Files for SelectMAP Configuration The .mcs file format is most commonly used to program Xilinx serial configuration PROMs that in turn programs a single FPGA in SelectMAP mode. For custom configuration solutions, the .bin and .hex files are the easiest PROM file formats to use due to their raw data format.
  • Page 56 Chapter 2: Configuration Interfaces www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 57: Chapter 3: Boundary-Scan And Jtag Configuration

    Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1 The Virtex-4 family is fully compliant with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The architecture includes all mandatory elements defined in the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP controller, the instruction register, the instruction decoder, the Boundary-Scan register, and the bypass register.
  • Page 58 TMS has an internal resistive pull-up to provide a logic High if the pin is not driven. Test Clock. This pin is the JTAG Test Clock. TCK sequences the TAP controller and the JTAG registers in the Virtex-4 devices. Notes: 1.

  • Page 59: Tap Controller

    Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1 TAP Controller Figure 3-2 diagrams a 16-state finite state machine. The four TAP pins control how data is scanned into the various registers. The state of the TMS pin at the rising edge of TCK determines the sequence of state transitions.
  • Page 60 TMS at the time of a rising edge at TCK. ug071_34_121703 Figure 3-2: Boundary-Scan Tap Controller Virtex-4 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports internal user-defined registers (USER1, USER2, USER3, and USER4) and configuration/readback of the device.

  • Page 61: Boundary-Scan Architecture

    Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1 Boundary-Scan Architecture Virtex-4 device registers include all registers required by the IEEE 1149.1 Standard. In addition to the standard registers, the family contains optional registers for simplified testing and verification (Table 3-2).

  • Page 62: Instruction Register

    Boundary-Scan instruction set is loaded into the Instruction Register. The length of the IR is device size-specific. The IR is 10 bits wide for all Virtex-4 LX, SX, and single-processor FX devices. FX devices with two processors have a 14-bit IR. The bottom six bits of the instruction codes are the same for all devices sizes to support the new IEEE Standard 1532 for In-System Configurable (ISC) devices.
  • Page 63 IR[4] IR[3] IR[2] IR[1:0] TDI → → TDO Reserved DONE INIT ISC_ENABLED ISC_DONE Figure 3-4: Virtex-4 Instruction Capture Values Loaded into IR as Part of an Instruction Scan Sequence Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 64: Bypass Register

    = the revision code f = the 7-bit family code (0001011 for Virtex-4 LX family, 0010000 for Virtex-4 SX family, 0001111 for Virtex-4 FX family) a = the number of array rows plus columns in the part, expressed in 9 bits:...
  • Page 65 Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1 Table 3-4: Virtex-4 Device JTAG ID Codes Device IDCODE Device IDCODE Device IDCODE XC4VLX15 XC4VFX12 01658093 01E58093 XC4VLX25 XC4VSX25 XC4VFX20 0167C093 02068093 01E64093 XC4VLX40 XC4VSX35 XC4VFX40 016A4093 02088093 01E8C093 XC4VLX60 XC4VSX55 XC4VFX60...

  • Page 66: Configuration Register (Boundary-Scan)

    USERCODE Register The USERCODE instruction is supported in the Virtex-4 family. This register allows a user to specify a design-specific identification code. The USERCODE can be programmed into the device and can be read back for verification later. The USERCODE is embedded into the bitstream during bitstream generation (BitGen -g UserID option) and is valid only after configuration.

  • Page 67: Configuring Through Boundary-Scan

    An individual Virtex-4 device can be configured through JTAG on power-up. If the Virtex-4 device is configured on power-up, it is advisable to tie the mode pins to the Boundary-Scan configuration mode settings: 101 (M2 = 1, M1 = 0, M0 = 1).
  • Page 68 Instruction Instruction Load Bitstream Abort Startup Correct? Synchronous (Clock five 1s on TMS) TAP Reset Load JSTART Instruction Startup Sequence Reconfigure? Operational ug071_40_073007 Figure 3-6: Device Configuration Flow Diagram www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...
  • Page 69 Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1 Single Device Configuration Table 3-6 describes the TAP controller commands required to configure a Virtex-4 device. Refer to Figure 3-2 for TAP controller states. These TAP controller commands are issued automatically if configuring the part with the iMPACT software.

  • Page 70: Reconfiguring Through Boundary-Scan

    Figure 3-7: Boundary-Scan Chain of Devices Reconfiguring through Boundary-Scan The ability of Virtex-4 devices to perform partial reconfiguration is the reason that the configuration memory is not cleared when reconfiguring the device. When reconfiguring a chain of devices, refer to...

  • Page 71: Boundary-Scan For Virtex-4 Devices Using Ieee Standard 1532

    Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1532 Load JSHUTDOWN. Go to the RTI state and clock TCK at least 12 times to clock the shutdown sequence. Proceed to the SHIFT-IR state and load the CFG_IN instruction again. Go to the SHIFT-DR state and load the configuration bits. Make sure the configuration bits contain the AGHIGH command, asserting the global signal GHIGH_B.

  • Page 72: Clocking Startup And Shutdown Sequences (Jtag)

    When configuring the device through JTAG, the startup and shutdown clock should come from TCK, regardless of the selection in BitGen. In IEEE 1532 configuration mode, the startup and shutdown clock source is always TCK. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 73: Configuration Flows Using Jtag

    Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1532 Configuration Flows Using JTAG Power-Up V cc > ? PROGRAM_B Load 64 bits of bitstream data Keep clearing PROGRAM_B? 1 TCK cycles Configuration memory End of Clear Configuration Data? memory once more...
  • Page 74 BYPASS ISC_Enabled ISC_Done End of Startup Modal State ISC_Accessed ISC_Complete Operational Operational System Disabled Active Output Start-up ug071_38_121703 Figure 3-11: Signal Diagram for Successful ISC Partial and Full Reconfiguration www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 75: Chapter 4: Frame Ecc Logic

    The syndrome bit is interpreted as follows: 0: no error. S[11] 0, S[10:0] ≠ 0: single bit (SED) error; S[10:0] denotes location of bit to S[11] 1, S[10:0] patch (indirectly). Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...
  • Page 76 0: 100000000001 -> 100000000010 -> 100000000100 -> 100000001000 -> 100000010000 -> 100000100000 -> 100001000000 -> 100010000000 -> 100100000000 -> 101000000000 -> 110000000000 -> 100000000000 -> www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 77: Chapter 5: User Access Register

    The USR_ACCESS register can be used to provide a single 32-bit constant value to the fabric as an alternative to using a block RAM or LUTRAM to hold the constant. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...
  • Page 78 Chapter 5: User Access Register www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 79: Chapter 6: Reconfiguration Techniques

    All configuration bits for this block to block logic Configuration Logic Functional Block (DCM or MGT) ds071_46_071505 Figure 6-1: Block Configuration Logic without Dynamic Interface Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 80: Fpga Fabric Port Definition

    Virtex-4 FPGA User Guide and the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide shows the signals and functions implemented for the specific blocks. In general, the port is a synchronous parallel memory port, with separate read and write buses similar to the block RAM interface.
  • Page 81 Virtex-4 FPGA Data Sheet. DCLK DRDY DADDR[m:0] DI[n:0] DO[n:0] ds071_44_123003 Figure 6-4: Write Timing with Wait States DCLK DRDY DADDR[m:0] DI[n:0] DO[n:0] ds071_45_031804 Figure 6-5: Read Timing with Wait States Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...
  • Page 82 DRDY is active. The earliest that DEN can go active to start the next port cycle is the same clock cycle that DRDY is active. Notes: 1. Input denotes input (write) to the DRP. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 83: Drp Dcm Implementation

    Multiply by 5 0004 0004h (0000000000000100) • • • • • • • • • • • • Multiply by 31 0030 001Eh (0000000000011110) Multiply by 32 0031 001Fh (0000000000011111) Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 84: Dynamic Phase Shifting Through The Drp In Direct Mode

    In addition to the phase shift modes already available in Virtex-II and Virtex-II Pro devices, the Virtex-4 FPGA has implemented a Direct Phase Shift Mode (DPSM). This allows the user to control the phase-shift delay line elements (tabs) directly. The DPSM can be accessed through either the standard Phase Shift (PS) interface or the DRP.

  • Page 85: Icap - Internal Configuration Access Port

    Configuration Registers through the SelectMAP Interface” for details. There are two ICAP sites in Virtex-4 devices: TOP and BOTTOM. The implementation has the two interfaces share the same underlying logic. The only difference between them is their location on the chip and the interconnect to which they can be connected. The two interfaces can never be active at the same time.
  • Page 86 Chapter 6: Reconfiguration Techniques www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 87: Configuration Memory Frames

    SelectMAP and JTAG interfaces. Configuration Memory Frames Virtex-4 configuration memory is arranged in frames that are tiled about the device. These frames are the smallest addressable segments of the Virtex-4 configuration memory space, and all operations must therefore act upon whole configuration frames. Virtex-4 frame...

  • Page 88: Configuration Control Logic

    Configuration overhead contributes to the overall bitstream size. Configuration Control Logic The Virtex-4 configuration logic consists of a packet processor, a set of registers, and global signals that are controlled by the configuration registers. The packet processor controls the flow of data from the configuration interface (SelectMAP, JTAG, or Serial) to the appropriate register.

  • Page 89: Type 2 Packet

    Write FDRI Frame Data Register, Input (write configuration data) 00010 Frame Data Register, Output register (read Read FDRO 00011 configuration data) Read/Write Command Register 00100 Read/Write Control Register 00101 Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 90: Command Register (Cmd)

    Begin Shutdown Sequence: initiates the shutdown sequence, disabling SHUTDOWN 1011 the device when finished. Shutdown activates on the next successful CRC check or RCRC instruction (typically an RCRC instruction). www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 91: Control Register (Ctl)

    ICAP Port Select. ICAP_SEL Top ICAP Port Enabled (default) Bottom ICAP Port Enabled Security Level. 00: Read/Write OK (default) SBITS 01: Readback disabled 1x: Readback disabled, writing disabled except CRC register Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 92: Frame Address Register (Far)

    I/Os active Frame Address Register (FAR) The Virtex-4 devices are divided into two halves, the top, and the bottom. Frames in the bottom half mirror images in the top half with the exception of the vertical HCLK rows that contain the global and regional clocks. The HCLK title bits are in the same order in the both of the top and bottom frames.

  • Page 93: Status Register (Stat)

    GTS_CFG_B All I/Os are placed in high-Z state All I/Os behave as configured End of Startup signal from Startup Block. Startup sequence has not finished Startup sequence has finished Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 94: Configuration Options Register (Cor)

    The FPGA waits on DONE that is delayed by one StartupClk cycle. Use this option when StartupClk is running at high speeds. DONE pin is open drain DRIVE_DONE DONE is actively driven High www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...
  • Page 95 Startup cycle to stall in until DCMs lock. 000: Startup cycle 1 001: Startup cycle 2 010: Startup cycle 3 LOCK_CYCLE 011: Startup cycle 4 100: Startup cycle 5 101: Startup cycle 6 111: No Wait Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 96: Bitstream Composition

    Type 1 write 1 words to COR 30012001 Data word 0 XXXXXXXX Type 1 write 1 words to ID 30018001 Device_ID 0167C093 Type 1 write 1 words to CMD 30008001 www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...
  • Page 97 NO-OP 20000000 Type 1 write 1 words to CMD 30008001 LFRM command 00000003 NO-OP 20000000 99 more NO-Ops Type 1 write 1 words to CMD 30008001 GRESTORE command 0000000A Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...
  • Page 98 Type 1 write 1 words to CMD 30008001 DESYNC command 0000000D 20000000 20000000 20000000 20000000 20000000 20000000 20000000 20000000 Type 1 NO OP 20000000 20000000 20000000 20000000 20000000 20000000 20000000 20000000 www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 99: Chapter 8: Readback And Configuration Verification

    FPGA-based system, or use iMPACT to perform JTAG-based readback verify. iMPACT, the device programming software provided with the ISE® tools, can perform all readback and comparison functions for Virtex-4 devices and report to the user whether there were any configuration errors. iMPACT cannot perform capture operations, although Readback Capture is seldom used for design debugging because the Chipscope™...

  • Page 100: Readback Command Sequences

    Readback Command Sequences Virtex-4 configuration memory is read from the FDRO (Frame Data Register - Output) configuration register and can be accessed from the JTAG and SelectMAP interfaces. Readback is possible while the FPGA design is active or in a shutdown state, although block RAMs cannot be accessed by the user design while they are being accessed by the configuration logic.

  • Page 101: Configuration Register Read Procedure (Selectmap)

    4, and back to write control after step 4, as illustrated in Figure 8-2. CS_B RDWR_B BUSY WRITE READ DATA[0:7] CCLK UG071_49_010807 Figure 8-2: SelectMAP Status Register Read Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 102: Configuration Memory Read Procedure (Selectmap)

    Each of these steps is performed by a single configuration packet except for step 1 and step 8. Synchronization (step 1) and the large FDRO read (step 8) are performed by a Type-1, Type-2 packet combination. Table 8-2 shows the readback command sequence. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...
  • Page 103 Write RCRC command 00000007 Type 1 write 1 word to CMD 30008001 Write DESYNC command 0000000D Type 1 NOOP word 0 20000000 Write Type 1 NOOP word 1 20000000 Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 104: Accessing Configuration Registers Through The Jtag Interface

    Readback and Configuration Verification Accessing Configuration Registers through the JTAG Interface JTAG access to the Virtex-4 configuration logic is provided through the JTAG CFG_IN and CFG_OUT registers. Note that the CFG_IN and CFG_OUT registers are not configuration registers, rather they are JTAG registers like BYPASS and BOUNDARY_SCAN. Data shifted in to the CFG_IN register go to the configuration packet processor, where they are processed in the same way commands from the SelectMAP interface are processed.
  • Page 105 Shift the first 9 bits of the CFG_OUT instruction, 1110001101 LSB first. (CFG_OUT) Shift the MSB of the CFG_OUT instruction while exiting Shift-IR. Move into the SELECT-DR state. Move into the SHIFT-DR state. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 106: Configuration Memory Read Procedure (1149.1 Jtag)

    Write the write CMD register header. Write the RCFG command to the device. Write the write FAR register header. g. Write the starting frame address to the FAR register (typically 0x0000000). www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...
  • Page 107 Move into the SHIFT-IR State. Shift the first 9 bits of the JSHUTDOWN 111000110 instruction, LSB first. Shift the MSB of the JSHUTDOWN instruction while exiting SHIFT-IR. Move to RTI. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...
  • Page 108 Shift the last bit of the FDRO register out of the CFG_OUT data register while exiting SHIFT- Move into the Select-IR state. Move into the Shift-IR State. End by placing the TAP controller in the TLR state. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 109: Configuration Memory Read Procedure (1532 Jtag)

    An ASCII file that contains only expected readback data, ASCII including the initial pad frame. No commands are included. Readback This file must be used with the .msd file. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...

  • Page 110: Verifying Readback Data

    The readback data stream is shown in Figure 8-4. Readback Data Pad Frame 1 frame Total number Frame Data device frames UG071_51_092807 Figure 8-4: Readback Data Stream www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...
  • Page 111 Another approach for verifying readback data is to compare the readback data stream to the frame data within the FDRI write in the original configuration bitstream, masking readback bits with the .msk file. Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017...
  • Page 112 Figure 8-6: Comparing Readback Data Using the .msk and .bit Files The .rba and .rbb files contain expected readback data along with readback command sets. They are intended for use with the .msk file. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

  • Page 113: Readback Capture

    IOB and CLB configuration columns by reading configuration memory through the readback process. Register values are stored in the same memory cell that programs the register's init state configuration, thus sending the GRESTORE command to the Virtex-4 configuration logic after the Capture sequence can cause registers to return to an unintended state.
  • Page 114 8-8) that is located in Slice X8Y15 is located at bit offset 100790. Note that captured DFF values, along with LUTRAM and SRL16 values, are stored in their inverted sense. www.xilinx.com Virtex-4 FPGA Configuration User Guide UG071 (v1.12) June 2, 2017...

Table of Contents

Save PDF