Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 53

11. In the new window, select Tools Run Tcl Script. In the Run Script window, navigate to
add_scm2.tcl in the extracted files and press OK. The SuperClock-2 Module Design
Sources and Constraints are automatically added to the example design
X-Ref Target - Figure 2-9
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Figure 2-9: Sources after Running add_scm2.tcl
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Chapter 2: Creating the GTH IBERT Core
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(Figure 2-9).
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