Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 69

10. When the Synthesized Design opens, select dbg_hub in the Netlist window, then select
the Debug Core Options tab in the Cell Properties window and change the
C_USER_SCAN_CHAIN* option to 3
X-Ref Target - Figure 3-11
11. In the Project Manager window, under Program and Debug, click Generate Bitstream.
Confirm the launching of implementation
X-Ref Target - Figure 3-12
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
(Figure
Figure 3-11: Debug Core Options for dbg_hub
Figure 3-12: Generate Bitstream
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Chapter 3: Creating the GTZ IBERT Core
3-11). Click File > Save Constraints.
(Figure 3-12).
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