Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 29

All GTZ transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with the Samtec BullsEye connectors.
connector pad, and
X-Ref Target - Figure 1-21
Figure 1-21: A — GTZ Connector Pad. B and C — GTZ Connector Pinout
The SuperClock-2 module provides LVDS clock outputs for the GTH and the GTZ
transceivers reference clock in the IBERT demonstration. For the GTZ IBERT demonstration,
the output clock frequency is preset to 255.00 MHz. See the description for connecting the
SuperClock-2 module,
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Figure 1-21 B and C show the connectors pinout.
page 10, for more details.
www.xilinx.com
Chapter 1: VC7222 IBERT Getting Started Guide
Figure 1-21 A shows the
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