Revision History - Xilinx Virtex-7 FPGA VC7222 Getting Started Manual

Revision History

The following table shows the revision history for this document.
Date Version
09/20/2013 1.0
09/24/2013 1.0.1
11/07/2013 2.0
01/22/2014 3.0
04/16/2014 4.0
06/12/2014 5.0
09/17/2014 5.1
10/09/2014 6.0
11/24/2014 7.0
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Initial Xilinx release.
Updated the Notice of Disclaimer, page 2..
Updated for Vivado® Design Suite 2013.3. Updated most figures in
VC7222 IBERT Getting Started
Design Sources File Hierarchy.
Out-Of-Context Module. The name of the project ZIP file changed to
rdf0297-vc7222-ibert-2013-3.zip. Replaced Figure 3-8, Set As Out Of Context
Module with Design Sources File Hierarchy screen. Deleted Figure 3-12, Edit the
Implementation Setting. Updated
links.
Updated for Vivado Design Suite 2013.4. Updated
Figure 1-14, Figure 1-15,
Figure 2-1, and Figure 3-5.
Updated for Vivado Design Suite 2014.1. Updated 30 graphics in Chapters 1, 2, and 3.
File lists changed under Extracting the Project
to rdf0297-vc7222-ibert-2014-1.zip. Launching the Vivado Design Suite
Software was changed to Setting Up the Vivado Design Suite in the
IBERT Demonstration, page 9
sections, and In Case of RX Bit Errors was added to both sections.
Updated for Vivado Design Suite 2014.2. Updated
Figure 1-19, Figure 1-20,
Figure 2-1, Figure 2-4, Figure
through Figure 3-5, Figure
programming information in
the SuperClock-2 Module, page
Viewing GTZ Transceiver
Changed cable quantity from two to one under Requirements. Added a note about
cable quantity in Running the GTZ IBERT
information in GTZ Transceiver Clock
cable use in Attach the GTZ Quad
connection in Figure 1-24
Updated for Vivado Design Suite 2014.3. Added BullsEye cable instructions to
GTH Transceiver Operation. Updated
Figure 1-19, Figure 2-2, Figure
and Figure 3-11.
Updated for Vivado Design Suite 2014.4. The ZIP project file name changed to
rdf0297-vc7222-ibert-2014-4.zip. The board revision changed from Rev B to
Rev 1 (Figure 1-1). Updated
Figure 2-8.
www.xilinx.com
Revision
Guide. Figure 1-31 and
Deleted Figures 2-12 and Figure 3-9, Synthesize
Appendix A, Additional Resources and Legal Notices
Figure 1-27, Figure 1-28,
Files. The ZIP project file name changed
and Running the GTZ IBERT Demonstration, page 28
Figure 1-23, Figure 1-27,
2-8, Figure 2-11, Figure
3-8, Figure 3-11. and Figure
Starting the SuperClock-2 Module, page 20
36. Updated Viewing GTH Transceiver Operation
Operation.
Demonstration. Updated clock connection
Connection. Added a Caution regarding BullsEye
Connector. Added a note about the cable
and before Figure 1-33. Replaced
Figure 1-10, Figure
2-4, Figure 2-8, Figure
Figure 1-10, Figure 1-19,
Chapter 1,
Figure 2-11 were renamed
Figure 1-11, Figure 1-13,
Figure 1-29, Figure 1-33,
Running the GTH
Figure 1-10, Figure 1-11,
Figure 1-30, Figure 1-33,
2-14, Figure 2-16, Figure
3-13. Added device
and
Figure 3-3.
1-11, Figure 1-14,
2-9, Figure 2-14, Figure
Figure 1-20, Figure 2-4, and
3-2,
Starting
and
Viewing
3-5,
2