Dram Control Register - Motorola MVME162FX Programmer's Reference Manual

DRAM Control Register

This register controls the parity checking mode and DRAM enable.
Note
ADR/SIZ
BIT 31
NAME
R/W
OPER
RESET 0
RAMEN
PAREN-PARINT
Do not enable parity unless it is supported by the
DRAM mezzanine. The present MVME162FX models
do not contain parity DRAM.
$FFF42048 (8 bits)
30 29 28
R/W R/W R/W
0 0
This bit enables the access of the DRAM. The DRAM
should be enabled after the DRAM Space Base
Address Register is enabled and the ROM0 bit has
been cleared. The DRAM Space Base Address
Register is located at $FFF42020 bits 31-16 and the
ROM0 bit is located at $FFF42040 bit 20.
PAREN PARINT
0
0
1
1
NONE means no parity checking. Parity errors are
not detected or reported. INTERRUPT means that
the MPU receives a parity interrupt if a parity error
occurs. The bus cycle is terminated with TA*, and
runs at the same speed as unchecked cycles.
CHECKED means that the cycle is terminated by
TAE* if a parity error occurs. Note that CHECKED
cycles lengthen the DRAM accesses by one clock
tick.
Programming Model
27 26
WWP PARINT
R/W R/W
0 0 PL 0 PL
MPU
0 NONE
1 INTERRUPT NONE
0 CHECKED
1 INTERRUPT CHECKED
25 24
PAREN RAMEN
R/W R/W
0 PL 0 PL
Alternate
NONE
CHECKED
3-47
3