Dmac Status Register - Motorola MVME162FX Programmer's Reference Manual

DMAC Status Register

ADR/SIZ
BIT 7
MLTO
NAME
OPER R
RESET 0 PS
This is the DMAC status register.
DONE
VME
TBL
DLTO
DLOB
DLPE
$FFF40048 (8 bits of 32)
6 5 4
DLBE DLPE DLOB
R R R
0 PS 0 PS 0 PS
This bit is set when the DMAC has finished
executing commands and there were no errors or the
DMAC has finished executing command because
the halt bit was set. This bit is cleared when the
DMAC is enabled.
When this bit is set, the DMAC received a VMEbus
BERR during a data transfer. This bit is cleared when
the DMAC is enabled.
When this bit is set, the DMAC received an error on
the local bus while it was reading commands from
the command packet. Additional information is
provided in bits 3 - 6 (DLTO, DLOB, DLPE, and
DLBE). This bit is cleared when the DMAC is
enabled.
When this bit is set, the DMAC received a TEA and
the status indicated a local bus time-out. This bit is
cleared when the DMAC is enabled.
When this bit is set, the DMAC received a TEA and
the status indicated off-board. This bit is cleared
when the DMAC is enabled.
When this bit is set, the DMAC received a TEA and
the status indicated a parity error during a DRAM
data transfer. This bit is cleared when the DMAC is
enabled. This bit is not defined for MVME162FX
implementation.
LCSR Programming Model
3 2 1
DLTO TBL VME
R R R
0 PS 0 PS 0 PS
2
0
DONE
R
0 PS
2-65