Tick Timer 3 and 4 Control Registers
Tick Timer 4 Control Register
ADR/SIZ
BIT
15
NAME
OVF3
OPER
R
0 PL
RESET
Tick Timer 3 Control Register
ADR/SIZ
7
BIT
NAME
OVF3
OPER
R
RESET
0 PL
CEN
COC
COVF
OVF3-OVF0 These bits are the output of the overflow counter.
$FFF4201C (8 bits)
14
13
12
OVF2
OVF1
OVF0
R
R
R
0 PL
0 PL
0 PL
$FFF4201C (8 bits)
6
5
4
OVF2
OVF1
OVF0
R
R
R
0 PL
0 PL
0 PL
When this bit is high, the counter increments. When
this bit is low, the counter does not increment.
When this bit is high, the counter is reset to zero
when it compares with the compare register. When
this bit is low, the counter is not reset.
The overflow counter is cleared when a one is
written to this bit.
The overflow counter is incremented each time the
tick timer sends an interrupt to the local bus
interrupter. The overflow counter can be cleared by
writing a one to COVF.
Programming Model
11
10
9
COVF
COC
R
C
R/W
0
0 PL
0 PL
3
2
1
COVF
COC
R
C
R/W
0
0 PL
0 PL
3
8
CEN
R/W
0 PL
0
CEN
R/W
0 PL
3-25