Sram Space Size Register; Table 3-7. Sram Size Control Bit Encoding - Motorola MVME162FX Programmer's Reference Manual

SRAM Space Size Register

ADR/SIZ
BIT 15
NAME
OPER R
RESET
SEN
SZ1-SZ0
$FFF42024 (8 bits)
14 13 12
R R R/W
0 PL
SRAM ENABLE must be set to a one before the
SRAM can be accessed.
The size bits configure the SRAM decoder for a
particular memory size. The following table defines
their use. Note that the table specifies the allowed bit
combinations for SZ1 - SZ0. Any other combinations
generate unpredictable results.
SZ1 - SZ0 are set equal to the SZ1 - SZ0 bits of the
DRAM/SRAM Options Register. SZ1 - SZ0 are
programmable to facilitate diagnostic software.

Table 3-7. SRAM Size Control Bit Encoding

SZ1 - SZ0
$0
$1
$2
$3
Programming Model
11 10 9
SEN SZ1
R/W R/W R/W
Memory Size
Reserved
512KB
1MB
2MB
8
3
SZ0
R/W
1 PL
3-31