Dmac Vmebus Requester - Motorola MVME162FX Programmer's Reference Manual

VMEchip2
2

DMAC VMEbus Requester

2-14
support the various port sizes and to allow transfers which are not
an even byte count or start at an odd address, with respect to the
port size. A 16-bit device should respond with VA<1> high or low.
Devices on the local bus should respond to any combination of
LA<3..2>. This is required to support the burst mode on the
MC68040 bus.
Normally when the non-increment mode is used, the starting
address and byte count would be aligned to the port size. For
example, a DMA transfer to a 16-bit FIFO would start on a 16-bit
boundary and would have an even number of 16-bit transfers. If the
starting address is not aligned or the byte count is odd, the DMA
controller will increment the lower address lines. This is required
because the lower order address lines are used to define the size of
the transfer and the byte lanes.
The VMEbus uses VA<2..1>, LWORD*, and DS<1..0>* to define the
transfer size and byte lanes. If the VMEbus port size is D32, then
VA<1>, LWORD* and DS<1..0>* are used to define the transfer size
and byte lanes. During D16 transfers, the VMEbus address line
VA<1> toggles. If the VMEbus port size is D64, then VA<2..1>,
LWORD* and DS<1..0>* are used to define the transfer size and
byte lanes. Local bus address LA<3..0> and SIZ<1..0> are used to
define the transfer size and byte lanes on local bus. During local bus
transfers, LA<3..2> count.
The DMA controller internally increments the VMEbus address
counter and if the transfer mode is BLT, the DMA controller
generates a new address strobe (AS*) when a block boundary is
crossed.
The chip contains an independent VMEbus requester associated
with the DMA Controller. This allows flexibility in instituting
different bus tenure policies for the single-transfer oriented master,
and the block-transfer oriented DMA controller. The DMAC
requester provides all the signals necessary to allow the onchip
DMA Controller to request and be granted use of the VMEbus.