Dma Arbitration Control Register - Motorola MVME162FX Programmer's Reference Manual

IP2 Chipming Model

DMA Arbitration Control Register

4
ADR/SIZ
BIT
NAME
OPER
RESET
PRI1 - PRI0
00
01
10
11
Programming Model
PRI1 - PRI0
00
01
10
11
4-30
The DMA arbitration control register contents determine whether a
fixed or fair arbitration algorithm is used to determine how the
MC68040 local bus is attached to the internal DMA data paths.
7 6
0 0
R R R
0 R 0 R 0 R
ROTAT set to a zero enables a rotating arbitration
ROTAT
method where each DMAC has equal access to the
MC68040 local bus. If ROTAT is set to a one, the
priority is fixed according to the following table
PRI1,PRI0 Fixed priority assignment is defined by the
following tables.
Priority with one DMA channel at IP sockets a, b, c, & d
Highest Next Highest
DMA_a
DMA_b
DMA_c
DMA_d
Priority with two DMA channel at IP sockets a and c
Highest Next Highest
DMA_a chan 0 DMA_a chan 1
DMA_a chan 1 DMA_c chan 0
DMA_c chan 0 DMA_c chan 1
DMA_c chan 1 DMA_a chan 0
$FFFBC01E (8 bits)
5 4 3
0 0 0
R R
0 R 0 R
Next Lowest
DMA_b DMA_c
DMA_c DMA_d
DMA_d DMA_a
DMA_a DMA_b
Next Lowest
DMA_c chan 0
DMA_c chan 1
DMA_a chan 0
DMA_a chan 1
2 1 0
ROTAT PRI1 PRI0
R/W R/W R/W
0 R 0 R 0 R
Lowest
DMA_d
DMA_a
DMA_b
DMA_c
Lowest
DMA_c chan 1
DMA_a chan 0
DMA_a chan 1
DMA_c chan 0