Bbram Interface; 82596Ca Lan Interface; Mpu Port And Mpu Channel Attention - Motorola MVME162FX Programmer's Reference Manual

The 28F008SA has a ready/busy pin to interrupt the processor
when certain commands have completed. The MC2 chip does not
utilize this feature. Software has to poll the status register to
determine device availability.
The MC2 chip ASIC supports write cycles to EPROM memory
space with a normal cycle termination by asserting transfer
acknowledge. Data is not changed. The MC2 chip allows the write
cycle to time out.
The Flash memory has a write-protect feature. A CSR bit in the
Flash Parameter Register (FWEN, bit 11) inhibits write cycles to
Flash.

BBRAM Interface

The MC2 chip provides a read/write interface to the BBRAM by
any bus master on the MC68040 bus. The BBRAM interface
operates identically to the Flash in that it performs dynamic sizing
for accesses to the 8-bit BBRAM to make it appear contiguous. This
feature allows code to be executable from the BBRAM. Burst
accesses to BBRAM are inhibited by the interface so that they are
broken into four longword accesses. The BBRAM device access
time must be no greater than 5 BCLK periods in fast mode or 9
BCLK periods in slow mode. The BBRAM speed option is
controlled by control bit 8 in the General Control Register at
address $FFF42000 in the MC2 chip.

82596CA LAN Interface

The LAN controller interface is described in the following sections.

MPU Port and MPU Channel Attention

The MC2 chip allows the MC68040 bus master to communicate
directly with the Intel 82596CA LAN Coprocessor by providing a
map decoder and required control and timing logic. Two types of
direct access are feasible with the 82596CA: MPU Port and MPU
Attention.
Functional Description
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