Registers - Motorola MVME162FX Programmer's Reference Manual

IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control

Registers

ADR/SIZ
7
BIT
NAME($10) a0_PLTY
NAME($11) a1_PLTY
NAME($12) b0_PLTY
NAME($13) b1_PLTY
NAME($14) c0_PLTY
NAME($15) c1_PLTY
NAME($16) d0_PLTY
NAME($17) d1_PLTY
OPER R/W
RESET 0 R
IL2-IL0
ICLR
IEN
INT
E/L*
PLTY
$FFFBC010 through $FFFBC017 (8 bits each)
6 5 4
a0_E/L* a0_INT a0_IEN
a1_E/L* a1_INT a1_IEN
b0_E/L* b0_INT b0_IEN
b1_E/L* b1_INT b1_IEN
c0_E/L* c0_INT c0_IEN
c1_E/L* c1_INT c1_IEN
d0_E/L* d0_INT d0_IEN
d1_E/L* d1_INT d1_IEN
R/W R R/W
0 R 0 R 0 R
These three bits select the interrupt level for the
corresponding IndustryPack interrupt request.
Level 0 does not generate an interrupt.
In edge-sensitive mode, writing a logic 1 to this bit
clears the corresponding INT status bit. In level-
sensitive mode, this bit has no function. It always
reads as 0.
When IEN is set, the interrupt is enabled. When IEN
is cleared, the interrupt is disabled.
When this bit is high, an interrupt is being generated
for the corresponding IndustryPack IRQ. The
interrupt is at the level programmed in IL2-IL0.
When this bit is high, the interrupt is edge sensitive.
When the bit is low, the interrupt is level sensitive.
When this bit is low, interrupt is activated by a
falling edge/low level of the IndustryPack IRQ*.
When this bit is high, interrupt is activated by a
Programming Model
3 2 1
a0_ICLR a0_IL2 a0_IL1
a1_ICLR a1_IL2 a1_IL1
b0_ICLR b0_IL2 b0_IL1
b1_ICLR b1_IL2 b1_IL1
c0_ICLR c0_IL2 c0_IL1
c1_ICLR c1_IL2 c1_IL1
d0_ICLR d0_IL2 d0_IL1
d1_ICLR d1_IL2 d1_IL1
C R/W R/W
0 R 0 R 0 R
0
4
a0_IL0
a1_IL0
b0_IL0
b1_IL0
c0_IL0
c1_IL0
d0_IL0
d1_IL0
R/W
0 R
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