Memory Maps; Local Bus Memory Map; Normal Address Range - Motorola MVME162FX Programmer's Reference Manual

Board Description and Memory Maps
1

Memory Maps

Local Bus Memory Map

Normal Address Range

1-8
Note that the
ABORT
GPI inputs to the VMEchip2, which are located at $FFF40088 bits
7-0, are not used. The
MC2 chip ASIC at location $FFF42043. The GPI inputs are
integrated into the MC2 chip ASIC at location $FFF4202C bits 23-16.
There are two points of view for memory maps: 1) the mapping of
all resources as viewed by local bus masters (local bus memory
map), and 2) the mapping of onboard resources as viewed by
VMEbus masters (VMEbus memory map).
The memory and I/O maps which are described in the following
tables are correct for all local bus masters. There is some address
translation capability in the VMEchip2. This allows multiple
MVME162FXs on the same VMEbus with different virtual local bus
maps as viewed by different VMEbus masters.
The local bus memory map is split into different address spaces by
the transfer type (TT) signals. The local resources respond to the
normal access and interrupt acknowledge codes.
The memory map of devices that respond to the normal address
range is shown in the following tables. The normal address range is
defined by the Transfer Type (TT) signals on the local bus. On the
MVME162FX, Transfer Types 0, 1, and 2 define the normal address
range. Table 1-2 is the entire map from $00000000 to $FFFFFFFF.
Many areas of the map are user-programmable, and suggested uses
are shown in the table. The cache inhibit function is programmable
in the MC68xx040 MMU. The onboard I/O space must be marked
cache inhibit and serialized in its page table. Table 1-3 further
defines the map for the local I/O devices.
switch logic in the VMEchip2 is not used. The
switch interrupt is integrated into the
ABORT