Dram And Sram Memory Controller Registers; Dram Space Base Address Register - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

DRAM and SRAM Memory Controller Registers

3

DRAM Space Base Address Register

ADR/SIZ
BIT
NAME
OPER
RESET
3-26
The DRAM decode logic consists of a base register, a size register,
and an options register. The SRAM decode logic consists of a
similar set of registers.
The reset logic initializes the DRAM and SRAM Base registers so
that DRAM space starts at address 0 and SRAM space starts at
$FFE00000. DRAM and SRAM are inhibited by reset. Software can
examine the MVME162FX DRAM/SRAM Options Register at
address $FFF42024 bits 20-16 to determine the size of the SRAM
and DRAM.
31 ...
B31-B20
R/W
0 PL
B31-B20 B31 - B20 are compared to local bus address signals
A31 - A20 for memory reference cycles. If they
compare, a DRAM cycle is initiated. Note that there
is linkage between the Base Address Register and its
associated Size Register. The Size Register masks the
least significant address signals for the comparison.
Therefore, the Base Address Register contents must
be set to a multiple of the Size Register. For example,
if the size is set for 4096KB, the Base Register must be
set to 0, or 4096KB, or 8192KB, or 12288KB, etc.
$FFF42020 16 bits)
20 19 ... 16
R
0