Lanc Bus Error; Lanc Interrupt; 53C710 Scsi Controller Interface - Motorola MVME162FX Programmer's Reference Manual

LANC Bus Error

The 82596CA does not provide a way to terminate a bus cycle with
an error indication. Bus error are processed in the following way.
The 82596CA interface logic monitors all bus cycles initiated by the
82596CA, and if a bus error is indicated (TAE* = 0 and TA* =1), the
Back Off signal (BOFF*) to the 82596CA is asserted to keep the
82596CA off the local bus and prevent it from transmitting bad data
or corrupting local memory. The LANC Error Status Register in the
MC2 chip is updated and a LANC bus error interrupt is generated
if it is enabled in the MC2 chip. The Back Off signal remains
asserted until the 82596CA is reset via a port reset command. After
the 82596CA is reset, pending operations must be restarted.

LANC Interrupt

The MC2 chip provides an interrupt control register for normal
LANC termination and another register for bus error termination of
LANC operation. The MC2 chip requests an interrupt at the level
programmed in the LANC interrupt control registers if the
interrupt is enabled and a positive edge is detected on the 82596CA
INT* pin or if the LANC bus error condition is detected.

53C710 SCSI Controller Interface

The MC2 chip provides a map decoder and an interrupt handler for
the NCR 53C710 SCSI I/O Processor. The base address for the
53C710 is $FFF47000. The MC2 chip requests an interrupt at the
level programmed in the SCSI interrupt control register if the
interrupt is enabled and a low level is detected on the 53C710 IRQ*
pin.
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