Mc2 Chip Revision Register; General Control Register - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

MC2 chip Revision Register

ADR/SIZ
3
BIT
NAME
OPER
RESET

General Control Register

ADR/SIZ
BIT
NAME
OPER
RESET
3-12
23 22 21
RV7 RV6 RV5
R R R
0 PL 0 PL 0 PL
RV7-RV0 The current value of the chip revision is $01. This
register is read only. It ignores a write but ends the
cycle with TA*, i.e., the cycle terminates without
exceptions.
15 14 13
R R R
0 PL 0 PL 0 PL
FAST This control bit tailors the control circuit for BBRAM
to the speed of BBRAM.
When operating at 25 MHz, the FAST bit should be
cleared for devices with access times longer than 200
ns (5 CLK cycles). The bit can be set for devices that
have access times of 200 ns or faster. It is not allowed
to use devices slower than 360 ns (9 CLK cycles), at
25 MHz.
When operating at 32 MHz, the FAST bit should be
cleared for devices with access times longer than 150
ns (5 CLK cycles). The bit can be set for devices that
have access times of 150 ns or faster. It is not allowed
to use devices slower than 270 ns (9 CLK cycles), at
32 MHz.
$FFF42000 (8 bits)
20 19
RV4 RV3 RV2
R R
0 PL 0 PL 0 PL
$FFF42000 (8 bits)
12 11
SCCIT1 SCCIT0 PPC
R/W R/W R/W
0 PL 0 PL 0 PL
18 17 16
RV1 RV0
R R R
0 PL 1 PL
10 9 8
MIEN FAST
R/W R/W
0 PL 0 P